Hard Ball
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- Jul 3, 2005
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Actually neither is true;
AMD will be producing 32nm server products in 2H10, and move desktop parts to 32nm in early 2011. So nothing has really changed, AMD is still lagging behind Intel in terms of the manufacturing front by the same margin as since the 65nm transition in Q4 of 05; when Intel shortened their process node from 90->65 to about 20 months.
Phynaz
Lifer
- Mar 13, 2006
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Actually if you look at the slides, 32 nm bulk silicon is planned to be in production in 2H10, the Radeon GPU's. Although not in the slides, AMD stated today SOI 32nm cpu's are planned for sometime in 2011.
"Allen also described for the first time AMD's plans for 32 nm processors it will now deliver in 2011."
I'd post the link to the EETimes article, but it keeps putting my session id in it. You should be able to find it.
As I was trying to say earlier, The Inq actually has it quite right...it's just being misinterpreted in this thread.
"these will come end of 2009, when the company begins the transition to 32nm"
As I said, it takes about 6 months for that transition, which puts production in H2 2010.
The Inq also said that it was to be bulk silicon first, followed by SOI.
The ATI chips are bulk, the CPUs are SOI (at least today).
Hard Ball
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Uhh, no;
There actually has been no definitive mention of the timing of the move to 32nm on MPUs overall today, that I am aware of. Today's information regarding the 32nm move centers around the arrival of the next-gen cores on 32nm for client platforms (orochi, llano, ontario); acutally said nothing about server MPUs at all, on when that would move to 32nm.
I have some preliminary information on bulldozer's microarchitecture from acquaintences in the industry, although it's a bit dated by now (about 12 months).
Phynaz
Lifer
- Mar 13, 2006
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Uhh..Yes
Third slide here.
Look under SOI - no dates.
Look under the bulk heading, "Ramp up on ATI Radeon GPUs planned"
Here's a better slide, 32nm cpus in 2011.
Third slide here.
Look under SOI - no dates.
Look under the bulk heading, "Ramp up on ATI Radeon GPUs planned"
Here's a better slide, 32nm cpus in 2011.
Hard Ball
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That is true; but quite irrelevant to the discussion here. No one is talking about that slide "tape outs accepted in late 2009 with early 2010 production ramp planned". But there is simply no mention of when MPU production on 32nm would begin, as far as I know.
I agree. I like AMD but, to announce a move to 32nm and you can't even get product released on time and competitive at 45nm is a waste of time. They have no credibility.
Does this put an end to the previously disclosed plan to release two variants of 45nm?
I haven't seen AMD discuss the move to 45nm HK/MG and ULK BEOL since those initial slides, and now it seems like all those plans have been pushed out to 32nm release.
edit: just came across this slide:
http://news.ati-forum.de/image...ski/News/2008/32nm.jpg
So that answers the question.
On a side note...anyone else look at the slide I linked and think it is kinda odd/sad that the technology highlight AMD has for their 45nm node is immersion litho? A tool and process you buy turnkey from a vendor, like the myriad of other tools purchased for the same?
Usually you try and highlight technology you actually invented yourself when you are assembling a slide titled "technology leadership roadmap". At least they showed they understand that desire given the process technology features highlighted for all the other nodes.
AMD: "the coolest thing about what we bring to the 45nm technology field is that we bought a commercially available scanner and we used it..."
I'm not sure what you mean here...AMD was the one of the first to go with immersion litho. Intel chose to hold on immersion litho until 32nm, so they still have the "hard yards" ahead of them.
What vendor sells a turnkey 45nm immersion litho line for SOI that fits into APM 3.0 systems?
I would have thought those were custom designed tools...am I wrong?
I'd like to make another point here...
As I said, for 45nm AMD went to their first generation of immersion litho, while Intel used double patterning of their existing 65nm process while adding HKMG.
For 32nm, it will be reversed...
AMD will be going with double patterning and adding HKMG, while Intel will be working their first immersion litho chips.
All in all, 32nm will be much tougher for Intel than it will be for AMD, but that says nothing about results...
You have to understand what litho is and does, it is invariant to substrate type. Bulk Si and SOI do not get different litho approaches. You do have different implant, etch, and cleans.
But again it is rather unusual to put a particular piece of equipment forward as your best feature of an entire process node. As I stated, look at the other node assets that AMD highlights and you can see (even without being a process development engineer) which of those things doesn't belong there.
As for the "hard yards" comment...it is true AMD was first (of the two) to implement Cu and low-k, but it certainly wasn't to Intel's detriment that they held onto Al and SiO2 for an extra node.
We can speculate whether Intel or AMD has more or less experience with immersion litho at this point, but consider AMD is releasing their immersion supported 45nm node nearly (or at least) a full year after Intel.
Had they released immersion 45nm the same time as Intel released double-pattern dry 193nm litho then you could have some merit pressing on the issue as a point of distinguishment between the two.
At any rate it is laughable to me that any company in this business would highlight a tool they purchased (one that anyone else can purchase from the same supplier) as the key technology attribute of their 4yrs of process development effort. Immersion litho is not something that makes any difference to the device's performance, it is entirely for improving yields (or decreasing the yield loss from litho passes as it were).
The fact that the integrated device from Intel's 45nm node contains HK/MG is what improves it's performance, not that it uses a disposable gate (replacement gate) with the metal gate added post CMP and poly-si strip. When you cut open a Shanghai chip and analyze the process technology you are not going to find a layer in there with a label saying "hi, thanks to immersion litho this part of my in the xtor is performing waaayy better, thanks for asking".
Uhg, this is turning into a pointless rant. I just wanted to make a passing observation, if anything a tinge of disappointment. It might be too much of an inside joke that only the handful of process development engineers here would get because it takes a backdrop of the work experience to communicate the funniness of it I suppose.
I love immersion litho (we had it at TI too, for 45nm deployment), if optimized and leveraged to its full potential it will improve yields and reduce cycle time. But it won't make 3GHz chips run at 4GHz and it won't make 100W processors consume 50W. HK/MG does that, ULK helps with that. Basically all the features they promised for 45nm that are now being pushed off to 32nm.
Phynaz
Lifer
- Mar 13, 2006
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You must not realize you don't use immersion lithography unless you have to.
Immersion lithography is a "have to do", not a "want to do". It's inherently more expensive.
The fact the Intel didn't have to use immersion at 45nm is a testament to their better process technology.
- Dec 30, 2006
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Remember when INTEL announced the new metal gates. IBM said ya me and AMD have that also .. Now after this amount of time I call BS on IBM and AMD was a victom.
I am still confused on the 32nm AMD thing . Bare with me.
in O9 NV ati are going to 40nm . seems to me if TSMC has the 32nm ready in late 09. I can't see ATI letting NV get the jump on them. 6 months would be bad. bad .
I am still confused on the 32nm AMD thing . Bare with me.
in O9 NV ati are going to 40nm . seems to me if TSMC has the 32nm ready in late 09. I can't see ATI letting NV get the jump on them. 6 months would be bad. bad .
Intel does a double-exposure, don't they? Isn't that pretty costly? Does it result in any additional design rules that adversely affect area?
- Dec 30, 2006
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Well Viditor thats the way I heard it also. But keep in mind Intel has already shown us 32nm sil. So maybe intel is ontop of this along time ago . Intel probably installed the equipment befor AMD. AT 45 intel choose to bring us 1 part of a 2 step plane. That being the easy part first HKMD. The second part being the harder to do . That being 3D gates . I am sure and will bet that AMDs 32nm HKMD will be better than Intels present HKMD. Pretty sure AMDs will be finfet that why intel will bring 3D gates at 32nm.
http://en.wikipedia.org/wiki/Double_patterning
The downsides to double-patterning are cost - your wafers have inherently higher cycle time owing to the extra processing steps.
To my knowledge the only IC-level performance impacting factor that can come from double-pattern is dependent on your alignment spec and allowed reworks...all of which comes back to cost if you decide to not let it impact performance. Don't want to deal with a lot of reworks from wafers failing your alignment spec then you just loosen the design rules for accepted variation in spacing (higher leakage, more CV capacitance variance, TDDB impact) and/or you loosen your pitch a tad (say 5nm) and loose a little of your areal scaling and clock propagation to buffer against the variability.
Or you tighten your alignment spec and allow for more photo reworks (adds cycle time...which adds costs and decreases yield). All of this is identical by the way to how the fabs manage single-exposure litho loops too, this isn't a new invention of management infrastructure with all the associated overhead.
When it comes to cost though you really have to ask the question which is costlier - delaying a 45nm shrink by 12 months in order to get your single-pattern immersion litho (expensive in its own right) yielding to entitlement yields while shipping 65nm product for those 12 months, or shipping 45nm product for 12 months with each wafer bearing an incremental cost structure associated with a handful of double-pattern steps.
Of course it really (naturally) comes down to risk management. Years ago very early in the 45nm development cycle when each company was setting about spice model targets the decision was made as to which litho technology would be pursued to enable the process to meet the spice targets that the design groups were using in parallel.
For TI, and AMD, the decision came down to pursuing immersion. For Intel, prolly because they were pursuing a timeline about 6 months ahead of us, they chose double-pattern. 6 months is a big difference in terms of equipment maturity and process maturity. Had AMD decided 4 yrs ago that 45nm would ramp to volume in Q1'08 then they probably would have decided immersion was just too risky/aggressive an item to jeopardize missing such a release timeline over.
- Dec 30, 2006
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I am tring to find recent info on AMDs finfet design . Not having much luck. I found this in my Word documents .Have know idea were it come from . I will keep looking for current FinFet for AMD.
Compared to today's planar transistors, tri-gate transistors use three gates instead of only one. According to Mike Mayberry, vice president and director of component research at Intel, the addition of two gates allows the company to increase the amount of current running through the transistor and decrease leakage since current can be routed into three different channels. First tri-gate transistors apparently have been manufactured and Mayberry claimed that 65 nm versions offer a 45% increase in speed or 50x reduction in "off"-current when compared to regular planar transistors.
Compared to today's planar transistors, tri-gate transistors use three gates instead of only one. According to Mike Mayberry, vice president and director of component research at Intel, the addition of two gates allows the company to increase the amount of current running through the transistor and decrease leakage since current can be routed into three different channels. First tri-gate transistors apparently have been manufactured and Mayberry claimed that 65 nm versions offer a 45% increase in speed or 50x reduction in "off"-current when compared to regular planar transistors.
It's funny how everyone ignores Nemesis's insane ramblings. The guy is so batshit insane he doesn't realize that nobody is paying any attention to his posts.
We are like a family here in the CPU forum, and every family has that one uncle who always seems like they are either over-medicated or need to be medicated.
But nonetheless you love them for who they are despite the crazy things they do and say.
It doesn't hurt to read the posts, although some times it does result in the reader screaming out "ohhh, mine eyez!".
It not that what gets posted is implausible, it's just that because what gets posted seems to be born from an ensemble of press release items it naturally tends to lack practicality when applied to the posited timeline...as with all marketing materials related to technology advancements; they usually (intentionally) lack the other half of the story which the engineers who work on such things already know about from their everyday experiences (but they can't publicly discuss for the obvious reasons).
I like reading the posts because it paints the corner condition of the absolute most aggressive technology cadence possible in the absence of fiscal responsibility as well as the absence of barriers that prove difficult to surmount once tackled. (think EUV, or projections of itanium revenue and market share)
To put it mildly, there are no rosier futures to contemplate than to read a Nemesis post, and who wants to crap on that by posting rebuttals? Tri-gates at 32nm? Sure, ok, bring it. Am I going to count on it? Not one iota, not anymore than I am counting on Finfet's coming at 22nm or CNT xtors at 16nm. We'll be on planar CMOS with HK/MG for the foreseeable future, but we can dream a little dream can't we? And in that dream Intel rolls 3D gates at 32nm, now then lets all drink some koolaid shall we?
But nonetheless you love them for who they are despite the crazy things they do and say.
It doesn't hurt to read the posts, although some times it does result in the reader screaming out "ohhh, mine eyez!".
It not that what gets posted is implausible, it's just that because what gets posted seems to be born from an ensemble of press release items it naturally tends to lack practicality when applied to the posited timeline...as with all marketing materials related to technology advancements; they usually (intentionally) lack the other half of the story which the engineers who work on such things already know about from their everyday experiences (but they can't publicly discuss for the obvious reasons).
I like reading the posts because it paints the corner condition of the absolute most aggressive technology cadence possible in the absence of fiscal responsibility as well as the absence of barriers that prove difficult to surmount once tackled. (think EUV, or projections of itanium revenue and market share)
To put it mildly, there are no rosier futures to contemplate than to read a Nemesis post, and who wants to crap on that by posting rebuttals? Tri-gates at 32nm? Sure, ok, bring it. Am I going to count on it? Not one iota, not anymore than I am counting on Finfet's coming at 22nm or CNT xtors at 16nm. We'll be on planar CMOS with HK/MG for the foreseeable future, but we can dream a little dream can't we? And in that dream Intel rolls 3D gates at 32nm, now then lets all drink some koolaid shall we?
Hard Ball
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Here is some more clarification on the situations, this is a good article on the subject matter from THG:
TG Daily; AMD unlikely to gain ground on Intel at 32 nm. Does it matter?
Allen with his usual bag of half-truths, especially in terms of the manufacturing side. As occurred before, there has been more promises of FUTURE shortening of process nodes that usually don't materialize as time progresses. In fact, the only time that timing has changed in last decade or so, where AMD process significantly shortened the gap was during the 250->180nm transition; and that they ceded back to Intel during the two successive transitions.
Also as noted, by and large, AMD introduces server parts on a new architecture or process node significantly before client parts; with a couple of notable exceptions (65nm transitions, partly because of the decision to focus on low cost 512K L2 parts and barcelona development and validation). And the current transition is no exception. This can range from sever parts preceding by a few weeks (SC -> DC Opteron in April 2005) to 5/6 months (Original K8 introduction).
The only clear roadmap for 32nm parts from AMD are the client MPUs on the next-gen execution core, there just isn't any clear information or guidance given about other product lines on that node.
It is pretty clear that they are specifically vague on the point of the next node transition, with the hope of shortening Intel's lead on this front; but not really confident about whether it can actually pull that off, and clearly does not want to repeat the same mistake in promises made about the 45nm node. The safest bet is really still during 2H10, but it is just to far off to know that with much certainty.
And even throwing more uncertainty into the equation, it is not really known at this time whether the final plan would be to introduce only the new microarchitecture on 32nm or would there be some server K10 derivatives that would be produced on the new node; that will make a significant difference if the new manufacturing node would actually be ready in earliest hoped timeframe.
THG is correct in concluding this, that AMD is intentionally reticent about its future plans for 32nm, and really went out of its way to make sure that no commitment about the 32nm transition be on the record for this Analyst meeting.
It is really beyond me that anyone in this forum can draw definitive conclusions about when the 32nm introduction would be, from a few slides on which AMD intentionally tried to keep mum about its 32nm introduction of performance SOI parts; especially given that AMD itself does not want to publicly commit to anything, and may not even know the precise timeframe. The slides about the 32nm bulk process is completely irrelevant to the discussion, and bears no way on MPU manufacturing one way or the other.
Edit: added link
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