Yes, they do indeed...and therefore it's easy to understand making the assumption that it was a direct shrink (hence my earlier comment about "Post Hoc Ergo Propter Hoc").
There are only 2 assurances that this isn't the case...
1. The die size wasn't reduced by half
2. The new L2 cache has a higher latency
While it's still a mystery as to what all of the changes were, we can be sure that changes were indeed made...
lots of reasons. electrical considerations is a big one, in deep submicron, transistor and wire characteristics don't exactly "scale" very well.
Those are certainly good reasons why a node shrink is difficult to do...but once you have a 45nm shrink, how can that be?
Edit: What I mean is that since 45nm is actually the distance from the far edge of one wire to the near edge of the next wire (inclusive of the wire of course), it seems to me that you are actually defining the area used with the node name (e.g. 45nm).
The only way that can change (it seems to me) is that you change the design...
yes, the design is changed, sometimes redone entirely. optical shrinks aren't done in the CPU industry now because the layout cannot be transformed from one process node to the next, the physical geometries won't map directly. and even if the process engineers came up with a process that matched exactly, chances are, the electrical differences will cause the design to run slower, or not at all, or only at a very narrow range. lots of possible issues.
That makes a lot of sense...thanks dmens. It also confirms what I've suspected of Brisbane all along, namely that it's lack of speed is a design issue and not a process issue. It also explains why AMD has been churning out new revs much faster than they normally do (4 different revs in 4 months) and why Barcelona was late...
True...but Virge's memory is quite right. There was a blurb about shrinkage in a Penryn article...
"While logic and cache structures generally end up scaling very well with a process shrink, I/O structures (e.g. main memory interface circuits) don't which is why the improvement in transistor density is roughly and not exactly 2x"
AT Penryn article
I think most people either don't know, or consider AMD "good enough". I think everyone else in my family uses Turion-based laptops and they're all happy with the battery life.
Scaling isn't as simple nowadays as it used to be. There are various design rules and complexities that cause some things to shrink slower than the ideal. If you can find some good high-res photographs (or this one) you could scale them to be the same absolute size and compare them. You can sometimes see interesting similarities and differences (PPro vs P3) doing comparisons like that.
You word that as if you believe some other company could do a pure (or almost-pure) optical shrink nowadays.... which makes me wonder about your claim to have worked on anything sub-130nm or so (or at least any remotely-aggressive designs).
Keep in mind that you can't compare the DDR1 dies to DDR2 dies.
No it isn't.
I'd be interested in comparing die photos to verify this. Not interested enough to do it myself, though
.So this means that eventually, the on chip I/O will begin to take a larger and larger part of processors as we get to smaller processes.
Doesn't sound good.
Doesn't sound good.
I don't believe that's correct TD...for example, AMD's 90nm had a drawn gate length of 50nm.
Middle of page
I'm fairly sure that Intel's 65nm products have a gate length of 35nm as well...
It's complicated, but it's still not what you think it is. The short version (ITRS definition) relates to the poly pitch in SRAM cells, but I forget their exact definition
.The first thing that I thought of was OPC (Optical Proximity Correction) but I can think of a few others. With OPC, because fabs are not reducing the wavelength of the laser used in lithography below 193nm, they end up producing fuzzy images. To clean up those fuzzy images, they add "artifacts" (some engineers that I know call them by the more technical term "Mickey Mouse ears"), those artifacts require increased spacing between poly than the minimum that you would like to use. This happens at any other layers that you want to OPC, and it trickles up the wiring layers. If you don't space them wider than you would like to, you can end up with shorts and other issues. When you don't shrink the spacing at the same rate as you shrink the other dimensions, you end up with a less than 50% shrink.
http://en.wikipedia.org/wiki/O...l_proximity_correction
http://www.cs.berkeley.edu/~ej...ork-0/results/gennari/
That said, moving from a dry litho to an shrunk immersion litho, it may be possible actually do better than a straight linear shrink since some of the more elaborate OPC artifacting can be reduced due to the improved numerical aperature. Although it depends obviously on how the immerision litho is implemented.
You are referring to "effective gate length" (AKA "leff") vs. "drawn gate length" (usually just "l" sometimes "ldrawn"). Lithography patterns the drawn gate, but then the source and drain creep under the drawn poly gate to reduce the "real" channel length down to less than drawn. Imagine the source and drain - which are defined by the gate - actually start to stretch out towards each other under the gate to make the real channel shorter. Effective channel length is a bit of a fuzzy area - I'm never quite sure if the people quoting their numbers are sure that those are the correct numbers - it's hard thing to figure out. Drawn can be measured on an electron microscope and is thus much more precise.
Effective channel length has an impact on the electrical characteristics of the FET.
Drawn channel length has an impact on both the electrical characteristics as well as the physical size of the device.
I'm sorry, I have to disagree here. A small shop called directron.com out of Houston has been selling a 5000+ black edition on 665nm since the start of this month.
That's certainly one factor, but I think others have a bigger effect. In particular, at the smaller process nodes, variability is going way up. This has a significant effect on dynamic circuits and other fancy circuits - in particular, SRAMs (register files, caches) and analog circuits (parts of the I/Os?). I'll focus on SRAMs because I don't know anything about the analog circuits.
An SRAM cell looks like this (also see this). A read is done by charging the wires on both "bit line" and "bit line bar" to VDD, and then raising the "word line". That turns the two access transistors on, and one of the bit lines will be pulled down. A write is done by setting one of the bitlines to VDD (depending on whether you're writing 1 or 0) and the other to 0, then raising the word line; the values on bit lines overpower the NOT gates and flip the cell. During a read, the powerful circuits that drive and "precharge" the bitlines are off, so the bitlines are controlled by the cell; during a write, the powerful drivers stay on to flip the cell.
When you're trying to write a bit cell, the NOT gates will fight against the write if the new value is different from the old one. In order for the write to actually occur, the access transistors have to be strong enough to overpower the NOT gates, and the trip point of the NOT gates (e.g. half way between 0 and VDD) have to be in the range that allows the write to happen.
When you're doing a read, you have to make sure that the cell doesn't get accidentally flipped. This could happen if the trip points of the NOT gates were very skewed. During the read, one of the NOT gates is driving a 0, but that node gets connected to a bitline that is at VDD. If the NOT gate isn't strong enough relative to the access transistor and the other NOT gate has a very low trip point, the node might bump up enough to flip the cell.
I'm sure both of those paragraphs were pretty confusing; it'd be clearer with pictures, but Linux has no good equivalent to MS Paint, so it'd take me a while to make anything decent.
Another potential problem can happen with a read. The way SRAMs work, you have many cells on each bit line. Smaller process nodes generally have leakier transistors. The access transistors leak, which can cause a problem: imagine bitlines with 1024 cells on them, and you're doing a read. Let's say there are 1023 cells storing 0, and 1 cell storing 1. You try reading that 1 cell. You would expect that "bit line" would stay at VDD, and "bit line bar" would be pulled to 0. However, you have 1023 pass transistors that, while "off", are conducting a little current. If this current is enough, both bit lines will be pulled down, and you won't be able to figure out whether you have a 1 or a 0.
High variability is a problem because you have to come up with ratios for the transistor sizes that are robust enough to yield well, and as the variation goes up, this becomes harder. The main way to address this is by using larger transistors for these sensitive circuits - bigger transistors vary less than small ones. However, as variability gets worse, you have to use relatively larger and larger transistors in these circuits.... so they don't shrink as fast as normal logic.
"Dynamic logic" is another problem.... but I think it requires another post.
Hopefully that was clear enough to understand without sacrificing much accuracy.
Immersion definitely helps with printing; I think Intel's 45nm parts are actually manufactured using double exposures which is another method (a time-consuming one, though) of making it possible to print smaller shapes. Better printing probably (educated guess - I really don't know) helps with some sources of variation like line edge roughness, but it won't help with other sources (the fact that there are only a few hundred dopant atoms, so it doesn't take many to significantly shift the threshold voltage).
IntelUser2000
Elite Member
- Oct 14, 2003
- 8,686
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http://www.dailytech.com/article.aspx?newsid=5984
"We'll be producing early products probably in Q2 of 2008, with full production in the second half."
Same thing Intel said for Penryn, except they said Q2 of 2008. But the product is coming in November.
Basically this is how I am getting to interpret the marketing departments.
First stage: "We are on track for production ramp"
Meaning a year away from production ramp to actual product
Second stage: "We are ramping up xxnm devices/producing devices"
Meaning its 6 months away from what they claim
Third stage: "We are now shipping devices"
Its very close to actual product launch.
In fact, its 2 years from one process tech to another. The companies might say whatever they want, but to the end users, nothing really changed. Intel takes two years from one process tech product to next gen process tech product, and AMD takes similar amount of time.
Well, you have to keep in mind that predictions in the article were from early Feb...
AMD used the same terminology when they released 65nm. The started the first production chips in June of 06 and started releasing volume production chips in Dec 06 (so 6 months is pretty much spot on). Since they are now starting production chips on 45nm, we can probably expect to see them in the April/May time period...
There is a caveat to this however. If AMD is unable to resolve their current design issues on K10 (though this may already have been done), then we may very well see a delay to 45nm as well...
It seems to me that AMD is late by a quarter on K10, but early by a quarter on 45nm (I didn't expect them to start 45nm production chips until Jan). This is probably due to the pressure Intel placed on them by coming out a quarter early on Penryn.
Another interesting thought I had was that AMD may very well have scrapped their plans to make Fab38 (the converted Fab 30) a 65nm Fab altogether and be starting it at 45nm.
If this is true, then AMD's 65nm process will be the shortest one they've ever had.
TuxDave
Lifer
- Oct 8, 2002
- 10,571
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I'm 100% sure that I'm correct. There's several metrics to note:
Drawn gate length (determines the technology node) is basically what the mask designer sees when drawing a minimum width gate. However the gate is not just a flat object but exists in 3D so what they do is taper down the gate so that by the time it hits silicon, it may actually be smaller. And due to diffusion seeping in underneath the gate from the source and drain you get an even smaller length called the effective channel length. But when I say "drawn gate length" that is not the effective gate length but the minimum pitch poly that we draw as seen from the top of the gate.
Careful with the terminology. The poly pitch (distance from the center of one poly to the center of the next) is different from the poly width / gate length. There are reasons the spacing (pitch) has to be more (See slide 37 here for some numbers - unfortunately I couldn't find the pitches for stacked devices (where you don't have to fit a contact between the two strips of poly)).
edit: here
TuxDave
Lifer
- Oct 8, 2002
- 10,571
- 3
- 71
Err yeah, sorry I toss the word pitch around sometimes when I shouldn't. I blame the people around me who toss around the word pitch randomly. But yeah, I meant poly width. In most of the non-secret processes I've worked on, at least on the 90nm node, the poly pitch is 180nm with the poly width of 90nm. But yeah, seeing the design rules at more agressive rules, I understand that things get a little crazy with the spacing.
did i get a faulty 65nm brisbane then? because even with a crap onboard video mobo
it hit 2.9@ stock voltages,3.0 with .07 volts increase.1.39vcore
it hit 2.9@ stock voltages,3.0 with .07 volts increase.1.39vcore
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