AMD 45nm in production now

[Regs]

So what about Phenom?

 

[bryanW1995]

sorry, they're both black editions. the 6400+ doesn't have an unlocked multi but it's clocked higher at 16x200, the 5000+ has an unlocked multi but it's stock clock is 13x200. They decided not to further cheapen their fx brand with more 4x4 or similar crap, so they had to come with some new marketing gizmos. I guess the 6400+ idea was so successful they copied themselves on the 5000+...

what about phenom regs? I curious to see what phenom x2 clocks up to. If they can get it closer to 3ghz then they'll be instantly competitive with c2d on the dual core platforms at least. unfortunately, K8 is so cheap right now that it seems highly unlikely it'll go down much more.

 

[Regs]

Originally posted by: bryanW1995

what about phenom regs? I curious to see what phenom x2 clocks up to. If they can get it closer to 3ghz then they'll be instantly competitive with c2d on the dual core platforms at least. unfortunately, K8 is so cheap right now that it seems highly unlikely it'll go down much more.

It's hard to take AMDs word of success on 45nm when they are launching 1.9 GHz 65nm Barc's and Phenom 2-4 months after. Just seems hard to believe. Though not every manufacturing process is the same, I know, maybe AMD will have better luck with 45nm for both the Barc and their next generation processors.

 

[CTho9305]

Originally posted by: bryanW1995
that would be a waste to go 45nm without changing to the high k metal gates. unless they just need a little die shrink to up their speed. of course, with all the problems they've had getting 65nm to run over 2.7, it doesn't make a lot of sense that they would magically get a much higher number out of 45nm. The high-k materials are an integral part of the 45 nm process, I think that you're just reading too much into that statement.

Someone has misled you. High-k is a "nice to have" at 45nm, in that it allows you to make the gate oxide thicker without hurting performance, improving gate leakage. Gate leakage has been increasing rapidly on modern processes, so high-k will soon be a "must have" (if you want to have any chance of producing competitive products), but it's still less of a problem than normal subthreshold leakage (here's a slide I found - note that those curves will be different for each manufacturer's process and could be different even for designs in chips at the same fab; this slide is also 4 years old). At some point, that will change, but 45nm is not that point. From a business perspective, even if a new process is no faster, it's a HUGE cost savings since you can fit about 2x as many on each wafer, lowering the per-die cost substantially. From a performance perspective, even if gate leakage doesn't substantially improve, you still get some of the normal scaling benefits (e.g. reduced gate cap which translates to dynamic power savings, some transistor speedup, etc). Intel did get 45nm out the door earlier than others, but they're apparently doing dry litho with double exposure, which does increase the per-unit cost (eating into the gains).

You have to be careful with drawing conclusions from certain types of documents. Press releases are a often a pretty bad source; even things like the "research@intel blog" can lead you to mistaken conclusions (even as a CPU guy, I think their post "Real Time Ray-Tracing: The End of Rasterization?" was not a fair comparison of the two techniques).

 

[Viditor]

Originally posted by: bryanW1995
that would be a waste to go 45nm without changing to the high k metal gates. unless they just need a little die shrink to up their speed. of course, with all the problems they've had getting 65nm to run over 2.7, it doesn't make a lot of sense that they would magically get a much higher number out of 45nm. The high-k materials are an integral part of the 45 nm process, I think that you're just reading too much into that statement.

Actually, I agree with jones on that one...my own interpretation is that they currently aren't using HK-MG on their 45nm process. That said, one of the benefits that IBM/AMD listed in their white paper on the process is that it's a very easy process to initiate. Remember that it's a very different process than Intel's, though the results are reputedly very similar...
I also agree with Ctho that it really isn't that critical...yet.

Edit: Further on the HK-MG process for those that are interested...
IBMeye blog

"Another huge benefit to the Hafnium Solution is that it can be implemented without requiring major tooling or process changes in manufacturing"

phynaz, it doens't make sense for amd to continue making 90nm chips when the 65 nm ones are so much cheaper to make. they've gotten up to 2700 mhz already, it seems entirely likely that they'll be able to run 3.0+ very soon at 65 if they're not there already. As others have said, it takes a few months to get from production to your doorstep. Well, maybe not "your" doorstep as you would clearly rather be paying intel $4,000 for an octal coare nehalem C in 3 yrs than have amd at least keep them honest.

Viditor, this whole topic is based upon statements made by amd execs who are continuing to try to stem the bleeding. They did better than most people expected and only posted an operating loss of $224 million. of course, it was closer to $400 million after one time charges/ati merger were factored in. AMD continues to point to the future because their "right now" is getting its ass whupped by big blue. For many years AMD has had a stranglehold on knowledgeable performance enthusiasts but they've now completely lost it. Just like somebody guying an 8600gt because nvidia dominates the "high end", more and more people are now jumping back to intel even for similarly-priced computers because of their newfound dominance. AMD keeps pointing to a moving future target in hopes that it will get wall street off them RIGHT NOW. Unfortunately, nehalem will be here a full year before fusion, so it's about to get much, much worse.

I think I'll start a new thread for the reply to this as it will be a long, involved, and a somewhat OT point for this thread...let me say though that there's a difference between an exec making a statement, and an exec making a statement in the CC.
Both Intel and AMD must always point to the future (AMD with 45nm, Shanghai, and Fusion, and Intel with Penryn and Nehalem)...and remember that AMD is still kicking Intel's butt in a few areas as well (Enterprise servers where they still have a lock on MP systems, and mobile where they have increased their sales by 41% over Q3 06).

 

[bryanW1995]

thanks for the info, ctho. The other day I read an interview with several of the intel engineers who actually worked on the high-k solution. I can't find the link here since I'm on wifey's laptop in the hospital, but iirc they implied that they couldn't thin out the gates any more so there would at best be limited improvement of going to 45nm without using high-k. you certainly have better access to this type of info, however, so I will bow to your superior knowledge

viditor, I thought that intel was killing amd in mobile. was amd's increase just due to a particularly bad q3 06, did they drastically lower laptop prices in search of market share, or did they come up with something significantly better than their previous offerings?

 

[Viditor]

Originally posted by: bryanW1995
thanks for the info, ctho. The other day I read an interview with several of the intel engineers who actually worked on the high-k solution. I can't find the link here since I'm on wifey's laptop in the hospital, but iirc they implied that they couldn't thin out the gates any more so there would at best be limited improvement of going to 45nm without using high-k. you certainly have better access to this type of info, however, so I will bow to your superior knowledge

viditor, I thought that intel was killing amd in mobile. was amd's increase just due to a particularly bad q3 06, did they drastically lower laptop prices in search of market share, or did they come up with something significantly better than their previous offerings?

Hey Bryan...

The increase is ironically due to the ATI acquisition. It seems that the new laptop chipsets are making huge inroads because they are cheaper and graphically far superior to Intel's current laptop platforms.
I agree that Intel's CPU's for laptops are as good as it gets, but their platforms are sorely lacking in all but the highest end. (and by highest end I refer to the nVidia chipsets for mobile workstations)

 

[bryanW1995]

that makes sense. I'm using my wife's A64 3200+ mobile system on an amd mobility radeon xpress 200 graphics chipset. it hasn't had any problems with older games that I've used on it when I was locked out of the house/traveling/etc.

of course, it's a good thing that I haven't tried anything too demanding on it since it is comparable to a geforce 5200...

 

[Viditor]

Originally posted by: bryanW1995
that makes sense. I'm using my wife's A64 3200+ mobile system on an amd mobility radeon xpress 200 graphics chipset. it hasn't had any problems with older games that I've used on it when I was locked out of the house/traveling/etc.

of course, it's a good thing that I haven't tried anything too demanding on it since it is comparable to a geforce 5200...

That sounds about right (though current AMD laptops use mobility x300 and x800 based systems).
I wouldn't count Intel out though...they have the better CPU currently, and as much as AMD is scrambling to get Barcelona improved, you can bet that Intel is doing the same with their mobile platform's graphics. After all, they basically invented the idea of a branded mobile platform with Centrino (and they were incredibly successful too!).

 

[hans007]

Originally posted by: bryanW1995
that would be a waste to go 45nm without changing to the high k metal gates. unless they just need a little die shrink to up their speed. of course, with all the problems they've had getting 65nm to run over 2.7, it doesn't make a lot of sense that they would magically get a much higher number out of 45nm. The high-k materials are an integral part of the 45 nm process, I think that you're just reading too much into that statement.

phynaz, it doens't make sense for amd to continue making 90nm chips when the 65 nm ones are so much cheaper to make. they've gotten up to 2700 mhz already, it seems entirely likely that they'll be able to run 3.0+ very soon at 65 if they're not there already. As others have said, it takes a few months to get from production to your doorstep. Well, maybe not "your" doorstep as you would clearly rather be paying intel $4,000 for an octal coare nehalem C in 3 yrs than have amd at least keep them honest.

Viditor, this whole topic is based upon statements made by amd execs who are continuing to try to stem the bleeding. They did better than most people expected and only posted an operating loss of $224 million. of course, it was closer to $400 million after one time charges/ati merger were factored in. AMD continues to point to the future because their "right now" is getting its ass whupped by big blue. For many years AMD has had a stranglehold on knowledgeable performance enthusiasts but they've now completely lost it. Just like somebody guying an 8600gt because nvidia dominates the "high end", more and more people are now jumping back to intel even for similarly-priced computers because of their newfound dominance. AMD keeps pointing to a moving future target in hopes that it will get wall street off them RIGHT NOW. Unfortunately, nehalem will be here a full year before fusion, so it's about to get much, much worse.

it would still be worth it even without high-k just to have smaller dies. a x4 phenom would probably be 180mm2 or less at 45nm (it is 280 something at 65nm)

 

[Viditor]

Originally posted by: hans007


it would still be worth it even without high-k just to have smaller dies. a x4 phenom would probably be 180mm2 or less at 45nm (it is 280 something at 65nm)

A good point hans...in fact if it's merely a pure node shrink, I'd say it would be closer to 150mm2.

 

[Phynaz]

Originally posted by: Viditor

Originally posted by: hans007


it would still be worth it even without high-k just to have smaller dies. a x4 phenom would probably be 180mm2 or less at 45nm (it is 280 something at 65nm)

A good point hans...in fact if it's merely a pure node shrink, I'd say it would be closer to 150mm2.

What makes you think they would achive this kind of scaling going to 45nm, when they didn't achive it going to 65 nm?

 

[Viditor]

Originally posted by: Phynaz

Originally posted by: Viditor

Originally posted by: hans007


it would still be worth it even without high-k just to have smaller dies. a x4 phenom would probably be 180mm2 or less at 45nm (it is 280 something at 65nm)

A good point hans...in fact if it's merely a pure node shrink, I'd say it would be closer to 150mm2.

What makes you think they would achive this kind of scaling going to 45nm, when they didn't achive it going to 65 nm?

A fair question...and frankly I don't know the reason. From a pure calculations perspective, a node shrink from 90nm to 65nm (assuming nothing is changed or added) should result in a 52% change (i.e. the 65nm chip's size would be 52% of the 90nm chip' size). I can only assume that AMD made other changes that I'm unaware of when they did it.
Are you aware of the reason?

Edit: Just had a thought...could it be that they reduced the number of layers at the same time? This would seem to be a logical explanation anyway (though I don't know if it's true...).

 

[Idontcare]

Originally posted by: Viditor

Originally posted by: Phynaz

Originally posted by: Viditor

Originally posted by: hans007


it would still be worth it even without high-k just to have smaller dies. a x4 phenom would probably be 180mm2 or less at 45nm (it is 280 something at 65nm)

A good point hans...in fact if it's merely a pure node shrink, I'd say it would be closer to 150mm2.

What makes you think they would achive this kind of scaling going to 45nm, when they didn't achive it going to 65 nm?

A fair question...and frankly I don't know the reason. From a pure calculations perspective, a node shrink from 90nm to 65nm (assuming nothing is changed or added) should result in a 52% change (i.e. the 65nm chip's size would be 52% of the 90nm chip' size). I can only assume that AMD made other changes that I'm unaware of when they did it.
Are you aware of the reason?

Edit: Just had a thought...could it be that they reduced the number of layers at the same time? This would seem to be a logical explanation anyway (though I don't know if it's true...).

He's not asking why AMD didn't do a true geometric shrink in going to 65nm, he's asking why you feel justified in thinking that in light of their past inabilities to do geometric shrinks you still think they will magically pull one off for 45nm.

 

[Viditor]

Originally posted by: Idontcare

He's not asking why AMD didn't do a true geometric shrink in going to 65nm, he's asking why you feel justified in thinking that in light of their past inabilities to do geometric shrinks you still think they will magically pull one off for 45nm.

A couple of questions...

1. What gives you the idea that it was an "inability" at all?
2. What kind of shrink do you think it was then? By that I mean that if the very definition of a node shrink is "the distance that would make ½ the pitch between the two closest parallel running metal lines that occur in the first metal contact layer for the device" (from ITRS definition), then how do you NOT end up with a die that is 52% the size of an identical design at the next higher node?

My own thought was that they eliminated a layer or 2 and thus decreased the die size shrinkage...do you have a hypothesis?

Edit: BTW, obviously eliminating layers can be even more cost effective than reducing the die size...it all depends on the chip.

 

[ViRGE]

Originally posted by: Viditor

Originally posted by: Phynaz

Originally posted by: Viditor

Originally posted by: hans007


it would still be worth it even without high-k just to have smaller dies. a x4 phenom would probably be 180mm2 or less at 45nm (it is 280 something at 65nm)

A good point hans...in fact if it's merely a pure node shrink, I'd say it would be closer to 150mm2.

What makes you think they would achive this kind of scaling going to 45nm, when they didn't achive it going to 65 nm?

A fair question...and frankly I don't know the reason. From a pure calculations perspective, a node shrink from 90nm to 65nm (assuming nothing is changed or added) should result in a 52% change (i.e. the 65nm chip's size would be 52% of the 90nm chip' size). I can only assume that AMD made other changes that I'm unaware of when they did it.
Are you aware of the reason?

Edit: Just had a thought...could it be that they reduced the number of layers at the same time? This would seem to be a logical explanation anyway (though I don't know if it's true...).

For whatever damn reason (I'm not privy to the technical details), not all features of a processor shrink the same; some features will end up larger than 52%. If you search AnandTech, I think one of the Penryn articles mentions this oddity.

Of course AMD's problem won't be the shrinkage, it's going to be what speeds they can clock their chips at. 65nm was more or less a disaster, they can't afford a repeat at 45nm.

 

[Viditor]

Originally posted by: ViRGE
For whatever damn reason (I'm not privy to the technical details), not all features of a processor shrink the same; some features will end up larger than 52%. If you search AnandTech, I think one of the Penryn articles mentions this oddity.

Of course AMD's problem won't be the shrinkage, it's going to be what speeds they can clock their chips at. 65nm was more or less a disaster, they can't afford a repeat at 45nm.

I think you're referring to the I/O structures (things like the memory interface and HT).
The die shot here shows which parts those are (the outer edges basically).
That's why it's ~52% instead of 50%...the I/O does shrink, but not as much as the logic and cache circuits.

As to clockspeed, that appears to be more of a design issue than a process issue.
Notice that AMD are releasing 2 different revs for Barcelona...one is for lower clockspeed and low power (Rev BA which is out now) and the other is for high clockspeed (Rev B2 at the moment, but Rev B3 has been sent to OEMs for testing already).

 

[Phynaz]

Originally posted by: Idontcare

Originally posted by: Viditor

Originally posted by: Phynaz

Originally posted by: Viditor

Originally posted by: hans007


it would still be worth it even without high-k just to have smaller dies. a x4 phenom would probably be 180mm2 or less at 45nm (it is 280 something at 65nm)

A good point hans...in fact if it's merely a pure node shrink, I'd say it would be closer to 150mm2.

What makes you think they would achive this kind of scaling going to 45nm, when they didn't achive it going to 65 nm?

A fair question...and frankly I don't know the reason. From a pure calculations perspective, a node shrink from 90nm to 65nm (assuming nothing is changed or added) should result in a 52% change (i.e. the 65nm chip's size would be 52% of the 90nm chip' size). I can only assume that AMD made other changes that I'm unaware of when they did it.
Are you aware of the reason?

Edit: Just had a thought...could it be that they reduced the number of layers at the same time? This would seem to be a logical explanation anyway (though I don't know if it's true...).

He's not asking why AMD didn't do a true geometric shrink in going to 65nm, he's asking why you feel justified in thinking that in light of their past inabilities to do geometric shrinks you still think they will magically pull one off for 45nm.

Notice he still didn't answer the question?

 

[ViRGE]

Originally posted by: Viditor

Originally posted by: ViRGE
For whatever damn reason (I'm not privy to the technical details), not all features of a processor shrink the same; some features will end up larger than 52%. If you search AnandTech, I think one of the Penryn articles mentions this oddity.

Of course AMD's problem won't be the shrinkage, it's going to be what speeds they can clock their chips at. 65nm was more or less a disaster, they can't afford a repeat at 45nm.

I think you're referring to the I/O structures (things like the memory interface and HT).
The die shot here shows which parts those are (the outer edges basically).
That's why it's ~52% instead of 50%...the I/O does shrink, but not as much as the logic and cache circuits.

As to clockspeed, that appears to be more of a design issue than a process issue.
Notice that AMD are releasing 2 different revs for Barcelona...one is for lower clockspeed and low power (Rev BA which is out now) and the other is for high clockspeed (Rev B2 at the moment, but Rev B3 has been sent to OEMs for testing already).

The Barcy may have design issues that require further revisions, but their overall 65nm process is just poor for clockspeeds. The K8 is a solid design and AMD still can't get the 65nm K8 parts to clock as high as the old 90nm parts. I'd imagine the Barcy will be limited by the same process issues.

 

[bryanW1995]

that would explain why they're so gung-ho on coming out with 45nm asap.

 

[dmens]

Originally posted by: ViRGE
The Barcy may have design issues that require further revisions, but their overall 65nm process is just poor for clockspeeds. The K8 is a solid design and AMD still can't get the 65nm K8 parts to clock as high as the old 90nm parts. I'd imagine the Barcy will be limited by the same process issues.

ibm power 6 is on the same process and is clocking in the 4.5 ghz range. so it's most likely a design issue.

 

[Viditor]

Originally posted by: ViRGE
The Barcy may have design issues that require further revisions, but their overall 65nm process is just poor for clockspeeds. The K8 is a solid design and AMD still can't get the 65nm K8 parts to clock as high as the old 90nm parts. I'd imagine the Barcy will be limited by the same process issues.

There's a saying in Latin that goes "Post Hoc Ergo Propter Hoc" which means "after this, therefore because of this".
This is a common trap taught in Logic classes. The fallacy lies in coming to a conclusion based solely on the order of events, rather than taking into account other factors that might rule out the connection.

In this case, when AMD went to 65nm, they also changed the design of the L2 cache on Brisbane to allow for larger caches. Unfortunately, the new design also increased latency at the same time...but the issue isn't the 65nm process at all.

(Now that I think about it, the new cache design may be a good portion of the reason for the larger die size...)

 

[Idontcare]

Originally posted by: Phynaz

Originally posted by: Idontcare

Originally posted by: Viditor

Originally posted by: Phynaz

Originally posted by: Viditor

Originally posted by: hans007


it would still be worth it even without high-k just to have smaller dies. a x4 phenom would probably be 180mm2 or less at 45nm (it is 280 something at 65nm)

A good point hans...in fact if it's merely a pure node shrink, I'd say it would be closer to 150mm2.

What makes you think they would achive this kind of scaling going to 45nm, when they didn't achive it going to 65 nm?

A fair question...and frankly I don't know the reason. From a pure calculations perspective, a node shrink from 90nm to 65nm (assuming nothing is changed or added) should result in a 52% change (i.e. the 65nm chip's size would be 52% of the 90nm chip' size). I can only assume that AMD made other changes that I'm unaware of when they did it.
Are you aware of the reason?

Edit: Just had a thought...could it be that they reduced the number of layers at the same time? This would seem to be a logical explanation anyway (though I don't know if it's true...).

He's not asking why AMD didn't do a true geometric shrink in going to 65nm, he's asking why you feel justified in thinking that in light of their past inabilities to do geometric shrinks you still think they will magically pull one off for 45nm.

Notice he still didn't answer the question?

Indeed I did.

The question you posed is a fair one to ask. Not that you need me to say that, but am just adding weight to the validity of your questions.

I feel qualified to say this as I have the benefit of having personally been involved in the development of some 10 node shrinks (0.5um, 0.42um, 0.35um, 0.25um, 180nm, 130nm, 90nm, 65nm, 45nm, and the first year of 32nm development) at TI so I do happen to know a thing or two about such things.

So yes I knew why I asked my question with precisely the words I chose, as I suspect you too choose your words carefully as I have gathered from your other posts on this forum, and yes I very much noticed that he pretty much refuses to acknowledge the request to qualify his statement.

 

[Viditor]

Originally posted by: Phynaz


Notice he still didn't answer the question?

I thought I had...I shall be more direct then.

The assumption that the designs of the 65nm and 90nm chips are the same and therefore it's a simple node shrink is incorrect...therefore the question is meaningless.

It would be like asking "if the Moon is made of cheese, why is the price of cheese so high?"

 

[Viditor]

Originally posted by: Idontcare


Indeed I did.

The question you posed is a fair one to ask. Not that you need me to say that, but am just adding weight to the validity of your questions.

I feel qualified to say this as I have the benefit of having personally been involved in the development of some 10 node shrinks (0.5um, 0.42um, 0.35um, 0.25um, 180nm, 130nm, 90nm, 65nm, 45nm, and the first year of 32nm development) at TI so I do happen to know a thing or two about such things.

So yes I knew why I asked my question with precisely the words I chose, as I suspect you too choose your words carefully as I have gathered from your other posts on this forum, and yes I very much noticed that he pretty much refuses to acknowledge the request to qualify his statement.

Wonderful...but I noticed that (with your expertise) you didn't answer my question either.
Given a pure node shrink, how is it possible NOT to reduce the die by near 50%?
What can go wrong?
Given the definition of what a node shrink is, and allowing for the lowered shrinkage of the I/O circuits, what explanation is there other than a design change?