Arachnotronic
Lifer
- Mar 10, 2006
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They might want to save Ryzen 3000s for DDR5.
Another speculative:
2870(X) => 16-core Zen2 w/ DDR4
2850(X) => 14-core Zen2 w/ DDR4
2820(X) => 12-core Zen2 w/ DDR4
2800(X) => 10-core Zen2 w/ DDR4
At that point Ryzen 3K might as well be based on Milan.
https://www.anandtech.com/show/12710/cadence-micron-demo-ddr5-subsystem
This way they wouldn't have to do Ryzen 3K two times. Once for X470/B450 and another for X500s/B500s.
AMD is longer hampered at the 7nm FinFET plus node either. So, they can hop onto the 5nm FinFET at TSMC. Since, early on this year GlobalFoundries said they weren't going to do 5nm.
Ryzen 2800s => 7nm FinFET
Ryzen 3000s => 7nm FinFET+ or 5nm FinFET (7nm FinFET to 5nm FinFET all being the same node; standard cells are compatible. Full EUV with the most relaxed PDK do to less complexity.)
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That's just silly and for 12nm, AMD made the transition and barely one at that because it took minimal effort to move over to it instead of just another 14nm proccess and they spent no time in right sizing the die and just allowed more black space (not in the way their diagram shows but the point still stands). They wouldn't have done that if they were spending the whole time designing a secondary die that is now shuddered and they certainly wouldn't go through the testing and validation prior to sale for something they basically would only have one step above engineering samples to sell. AMD created the die they wanted in PR. It's out and we know what it is.
Sure they could also call it something completely different or try to jump over Intell and call it the 10700X. AMD has defined their naming scheme and has set precedence with Ryzen 2k. If Zen + is named Ryzen 2k, then Zen 2 is going to be Ryzen 3k.
Both of these suffer from the same issue. People who know so much that they can think about all the possible solutions but it ignores the two most important parts. 1. The general reality of AMD's situation. B.) What is mostly likely.
A 2800x might come out but its not a 10c part. I could buy something like a 10c TR2 but it would be numbered like a 2915X and would break a lot of rules regarding CCX parity. But that one is feasible even if it will never happen.
While I agree likely fake, there are other explanations. Like AMD experimenting with new packaging (putting two dice on one Ryzen socket chip, maybe there's some extra layer, like an interposer or something, as AMD is trialing a new one, possibly looking to make a bigger APU where they put a sizable GPU on there along with a full 8 core CPU die, or maybe they'd look to add HBM or something to function like a larger cache, or perhaps its a start on their "chiplet" design - with Ryzen being probably more advanced in this respect than their current GPUs due to having InfinityFabric - with the exception being Vega which is almost certainly too large to be able to do something like that).
This lets them try it out and if it works well they can release it as a real product, and it'll cause waves. If it doesn't then they don't release it and just use it for internal testing (maybe offer it as a trial solution for people that want to adopt EPYC, but need to see how they can work with the inter-die stuff before they make the full jump).
Why would they do that? They'll go to 3000 series for Ryzen 2, 4000 series for the refresh, and then 5000 series for Ryzen 3 although I have a hunch they'll call it Ryzen Gen 5 or something (which should bring DDR5, PCIe 5, and think there might have been another "5" - maybe the chipset). But this way its all 5s for when they make that move. We might see them add DDR5 controllers to the Zen 2 refresh (mostly for EPYC as when they move to 64 cores this would let them increase the bandwidth without increasing the memory channels; but this way there's options for cheaper DDR4 still, but DDR5 for those that need the extra bandwidth and can pay for it).
That will be interesting to see (if there's a 7nm EUV step before the move to 5nm or if they just get EUV up and running on 7nm but for production just implement it on the 7nm node; I personally think that it'll be the former and that we might see Zen 2 refresh be only for EPYC and Threadripper, but that will be when they make the move to 64 core; with them waiting to see how things shake out from there, meaning how much production EUV offers and if 5nm uses it entirely). I've speculated this before, but I think
This lets them try it out and if it works well they can release it as a real product, and it'll cause waves. If it doesn't then they don't release it and just use it for internal testing (maybe offer it as a trial solution for people that want to adopt EPYC, but need to see how they can work with the inter-die stuff before they make the full jump).
Why would they do that? They'll go to 3000 series for Ryzen 2, 4000 series for the refresh, and then 5000 series for Ryzen 3 although I have a hunch they'll call it Ryzen Gen 5 or something (which should bring DDR5, PCIe 5, and think there might have been another "5" - maybe the chipset). But this way its all 5s for when they make that move. We might see them add DDR5 controllers to the Zen 2 refresh (mostly for EPYC as when they move to 64 cores this would let them increase the bandwidth without increasing the memory channels; but this way there's options for cheaper DDR4 still, but DDR5 for those that need the extra bandwidth and can pay for it).
That will be interesting to see (if there's a 7nm EUV step before the move to 5nm or if they just get EUV up and running on 7nm but for production just implement it on the 7nm node; I personally think that it'll be the former and that we might see Zen 2 refresh be only for EPYC and Threadripper, but that will be when they make the move to 64 core; with them waiting to see how things shake out from there, meaning how much production EUV offers and if 5nm uses it entirely). I've speculated this before, but I think
- Jul 27, 2018
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Thanks to all who gave their input!!! I also learned a great deal by reading your comments since I am an enthusiast but not an engineer! Thanks!
StinkyPinky
Diamond Member
- Jul 6, 2002
- 6,909
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I particularly like this explanation from reddit, why not to put trust into such cinebench scores. Courtesy of -Viktoria
Overclocking the mold can probably put it above 50GHz. Rank amateurs...
I believe anything zen+ over 8 cores a die on 12 whatever from GF to be fake, but...
With all the uncertainty around 7 whatever size and several years out, I can imagine that AMD might have a GF backup plan with 12nm larger core plan. Might even be optimized for the 12... Could be a dual 6 core ccx or 5 ccx, but I doubt it. But with the cost and uncertainty around shrinks and GF wafer commitments and rumors around 48 core epics????
With all the uncertainty around 7 whatever size and several years out, I can imagine that AMD might have a GF backup plan with 12nm larger core plan. Might even be optimized for the 12... Could be a dual 6 core ccx or 5 ccx, but I doubt it. But with the cost and uncertainty around shrinks and GF wafer commitments and rumors around 48 core epics????
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