Discussion Ada/'Lovelace'? Next gen Nvidia gaming architecture speculation

[Aapje]

I disagree. The monolithic die is just because that is more efficient for a small chip.

 

[jpiniero]

The fact that we're seeing 3 different Navi dies, one of which is monolithic would seem to suggest to me that there are still some kinks to be worked out when it comes to designing MCM GPUs. Otherwise AMD would have just created a single Navi chiplet that could be used in any number necessary to hit a particular performance level.

Keeping relevant to this thread (heh), it's almost certainly N5 wafer costs and maybe on some level availability.

It does make me wonder if AD106 and AD107 are on N6 or some other node that's not N5.

 

[Mopetar]

I don't know. It's certainly possible that NVidia could split up the product line across multiple nodes, but it does mean a lot of additional design work since you can't just create a single design for N5 that will magically work if back-ported to N6 without some tweaking. If they were going to do that it would only be because they made a decision similar to the one during Turing where some of the lineup didn't have RT hardware. Of course that doesn't seem likely because they'd be walking back what they did with Ampere where it was included across the lineup, even in chips that would never use it due to performance concerns.

The more likely outcome would be using a single node and just having a staggered release schedule with smaller dies launching later in the product cycle. There were some rumors that they'd continue producing Ampere on Samsung for a while after the Lovelace launch, which makes sense if they'll only have their big dies available for the first several months. It took over 5 months for GA-106 to hit the market and GA-107 only came out another 3 months after that.

 

[jpiniero]

I don't know. It's certainly possible that NVidia could split up the product line across multiple nodes, but it does mean a lot of additional design work since you can't just create a single design for N5 that will magically work if back-ported to N6 without some tweaking.

It is only a measly 20% SM increase. Crazy as it sounds you shouldn't rule out some Samsung node either.

 

[Glo.]

Why nobody mentioned this?

https://twitter.com/x/status/1519873990093058049

"I must clarify that the current AD102 is NOT the original AD102. Ada Lovelace is no longer a simple Ampere refresh, although it was like this in the beginning."

 

[Karnak]

Because 'in the beginning' would mean something like back in 2020. I like him, but at this point he is just guessing.

Ada from now is most likely the same it has been since the whole of 2021. There were now special changes or secret sauce stuff like 10 months ago which means Ada is now more than just an Ampere refresh. That's just nonsense tbh.

 

[Glo.]

No, that is NOT what he means, at all .

Its just wording, but the sense of chronological order suggests that there were vast changes to the architecture.

Those changes may be the reason why the power went through the roof.

 

[jpiniero]

Those changes may be the reason why the power went through the roof.

More likely clock speeds.

 

[Aapje]

There is a substantial lead time, so I don't see much room for a full redesign, although they might have increased the number of cores.

 

[DooKey]

Why nobody mentioned this?

https://twitter.com/x/status/1519873990093058049

"I must clarify that the current AD102 is NOT the original AD102. Ada Lovelace is no longer a simple Ampere refresh, although it was like this in the beginning."

I like how he's covering for his initial mistake. I suspect all along Ada Lovelace was a new architecture. He may have been fed bad info. Take what he says with a grain of salt.

 

[Aapje]

I agree that this is probably just to cover up a mistake on his part. It's very plausible that Nvidia also worked on a refresh, like AMD is releasing with the 6x50 cards, but that they didn't deem it necessary.

 

[jpiniero]

I like how he's covering for his initial mistake. I suspect all along Ada Lovelace was a new architecture. He may have been fed bad info. Take what he says with a grain of salt.

Guess there's a fine line between a "new architecture" and a "simple refresh". If they went to 192 cores/SM plus the extra L2, is that really a new architecture? Maybe if they beefed up the RT engine?

 

[Saylick]

Guess there's a fine line between a "new architecture" and a "simple refresh". If they went to 192 cores/SM plus the extra L2, is that really a new architecture? Maybe if they beefed up the RT engine?

Hard to say, right? Nvidia called Pascal a new architecture but under the hood, it was more or less an updated Maxwell on a newer node, with higher clocks, better memory compression, and some added features for VR. No IPC gains or a revamp of the SM.

With Lovelace, I think we'll get updated tensor and RT cores, which warrants calling it a new architecture. The enlarged L2 cache and whatever capabilities it permits also warrants calling it a new architecture too, in my opinion.

 

[GodisanAtheist]

NV, not content to be beaten on any front by AMD, is now hellbent in building its own faster, sleeker, RTX On hype train

 

[Timmah!]

I like how he's covering for his initial mistake. I suspect all along Ada Lovelace was a new architecture. He may have been fed bad info. Take what he says with a grain of salt.

I am not sure what is he covering for. 11 months ago he posted that thing about Lovelace being 2,2x as fast as Ampere, RDNA 2,5x and Hopper 3x (since it was supposed to be chiplet-based). Was the "low" 2,2x estimation meant to imply Lovelace being only Ampere "refresh"? Cause i certainly did not read it that way.
And does this all mean now we shall expect higher performance jump than 2,2x?

 

[SmokSmog]

He told that
Lovelace 2,2x of GA102 and Navi31 2,5x of Navi21

But GA102 is at least 10% faster than Navi21 at 4K

So
2,2*1,1=2,42
So
Navi21 = 1x
GA102 = 1,1x
AD102 = 2,42x
Navi31 = 2,5x

 

[jpiniero]

He told that
Lovelace 2,2x of GA102 and Navi31 2,5x of Navi21

But GA102 is at least 10% faster than Navi21 at 4K

So
2,2*1,1=2,42
So
Navi21 = 1x
GA102 = 1,1x
AD102 = 2,42x
Navi31 = 2,5x

It'd be way too early for either to finalize clock speeds. I wouldn't read much into that statement.

 

[Timmah!]

Apparently RDNA3 might have 3+GHz and 92TFlops. If thats the case, i am pretty sure Nvidia will be shooting for similar numbers with AD102. Those cca 18000+ cores at 2,5GHz would give similar TFlops after all.

Since 3090 with its 36TFlops is pretty much almost 2x as fast as 2080Ti with 18TFlops at rendering, i am salivating at proposition of a card with almost 3x higher TFlops.

 

[xpea]

No, that is NOT what he means, at all .

Its just wording, but the sense of chronological order suggests that there were vast changes to the architecture.

Those changes may be the reason why the power went through the roof.

Kopite has good source but what he says is non sense. Lovelace architecture was frozen 10 months ago and nothing has changed since. It's not a trivial task to get these multi billion transistors dies and you can't update a design in the middle of the road, unless you want to delay the product by several months. So once frozen, you have to do algorithm validation, circuit design, xtor floor plan, AI optimization, RTL generation / tape out. AD102 Silicon came back 3 weeks ago. Another 4-6 months of debugging and qualification, and AD102 HVM should be ready for back to school launch

 

[GodisanAtheist]

Is it possible that NV was running a couple different archs teams against each other, the leaks are from Arch team A, but NV will be going with Arch team B's more moonshot design or something?

A company with as much to spend on R&D as NV must have their fingers in a bunch of pies, and we know they design variations on their arch for different markets.

Changing the arch name is like the simplest thing to do.

 

[Glo.]

Is it possible that NV was running a couple different archs teams against each other, the leaks are from Arch team A, but NV will be going with Arch team B's more moonshot design or something?

A company with as much to spend on R&D as NV must have their fingers in a bunch of pies, and we know they design variations on their arch for different markets.

Changing the arch name is like the simplest thing to do.

Or simply heavily OC'ed silicon, which is why the power went from 450W to 600W, for halo SKU, but standard version.

102 TFLOPs equals to 2.75 GHz on 18452 CUDA cores.

 

[moonbogg]

They should just quit messing around and charge between 5 and 10 grand for the entire lineup. Let's get these endless price hikes and product stack changes to their logical conclusion already.

 

[eek2121]

Or simply heavily OC'ed silicon, which is why the power went from 450W to 600W, for halo SKU, but standard version.

102 TFLOPs equals to 2.75 GHz on 18452 CUDA cores.

I am seriously doubting most of the rumors regarding clocks and TDPs.

My FTW3 3090 already has a large, unwieldily cooler. To add a 50% larger heat sink on top of that? To say nothing of lost slots, a GPU support bracket would be absolutely required and not every case supports the use of said brackets.

A 900W TDP? No way.

What I expect we will see is 2-2.2 Ghz tops unless NVIDIA has made huge efficiency gains. The possible mhz increase from the shrink from Samsung 8n to TSMC N5 will be offset by a much larger die.

If NVIDIA has made breakthroughs in power management or cooling, then maybe, but something tells me these GPUs aren’t going to be as fast as people think. The top tier may be 40-60% faster than a 3090. That is my guess.

 

[Aapje]

I expect that water cooling will become common for the 4090.

 

[igor_kavinski]

To add a 50% larger heat sink on top of that?

The top tier may be 40-60% faster than a 3090. That is my guess.

It could be some cleverly designed beefier cooler. And the huge amount of cache is going to guarantee huge gains.