800 Mhz P4's = no big deal?

[NightTrain]

Originally posted by: Jeff7181There is a limit to how high a FSB is useful, I'm asking what that limit is.

Read the article Oldfart linked.

In this case, the focus is more on balancing FSB and memory bandwidth rather than frequencies (although it is important to have frequencies that are in sync with one another in order to keep latencies as low as possible). The Pentium 4 features a 64-bit wide FSB interface, and we've already explained the frequencies this FSB can run at. Simple multiplication shows us that the 533MHz FSB can offer a maximum of 4.264GB/s of bandwidth. The 845PE chipset has a 64-bit DDR333 memory interface, offering a maximum of 2.664GB/s of memory bandwidth, and the 850E chipset has a 32-bit PC1066 RDRAM memory interface that provides at most 4.264GB/s of memory bandwidth. As you can see just by looking at the bandwidth numbers, the 850E chipset is perfectly balanced for the amount of bandwidth offered by the 533MHz FSB, which is why it is significantly faster than the 845PE.

The 800MHz FSB will offer no less than 6.4GB/s of bandwidth, which would require either a 32-bit PC1600 RDRAM memory interface (note that the PC1600 standard does not exist) or a 64-bit DDR800 memory interface (also a non-existant memory technology). Well, if you can't get faster memory, you widen the memory interface in order to increase bandwidth. Remember that bandwidth is the product of bus width and transfer rate, so if you can't improve the transfer rate, you increase the width of the bus. In the case of the upcoming 865 and 875 chipsets, Intel took the 64-bit DDR memory interface of the 845PE chipset and added a second 64-bit channel along with adding DDR400 support. A 128-bit memory interface (2 x 64-bit channels) with DDR400 memory now offers exactly 6.4GB/s of memory bandwidth, perfectly balanced with the 800MHz FSB, without using exotic memory technology or speeds that aren't readily available.

 

[Regs]

It just like the men who are short saying it's not the size that counts, but how you use it

Yeah look how Geforce FX is using its 500MHz core clock.

I'll use one word to sum up the Intel P4, latency.

 

[WarCon]

Ok clue me into what you mean by summing up the P4 in one word, "latency"?

 

[oldfart]

Originally posted by: Regs

I'll use one word to sum up the Intel P4, latency.

Well that explains everything!

 

[Richdog]

Originally posted by: SinfulWeeper
Why not make faster CPU's? AMD is getting so blown out of the water they had to resort to a lame PR rating.

It just like the men who are short saying it's not the size that counts, but how you use it ... the absolutely the dumbest thing I ever heard

That is exactly what AMD is 'saying'...

But don't get me wrong. If push comes to shove, I'd build an AMD system... even though it costs the same to build either way.

To be fair, the only reason AMD had to invent the PR rating was because Intel were taking advantage of the fact that Mr. Joe Average User doesnt know that the AMD processors can carry out more instructions per clock cycle, rendering them more efficient. People just look at Mhz and say "ooh, higher must be faster", which isnt always true. When AMD's 400Mhz FSB arrives the gap should close some more, but I think its only with the arrival of Clawhammer that we're going to see sparks fly.

 

[Jeff7181]

NightTrain, thanks for the info and explanation rather than just saying "this is how it is, accept it"

But still, nobody answered my question... and I highly doubt that running the CPU core frequency and bus frequency in sync is going to be better than running the bus frequency at half the core frequency. (my 1500x2 and 3000x2 statement) If you can prove me wrong feel free... I'd like to see proof that the CPU's core has such a high demand for memory bandwidth that there's no point of diminishing returns.

 

[Wurrmm]

Originally posted by: Jeff7181
NightTrain, thanks for the info and explanation rather than just saying "this is how it is, accept it"

But still, nobody answered my question... and I highly doubt that running the CPU core frequency and bus frequency in sync is going to be better than running the bus frequency at half the core frequency. (my 1500x2 and 3000x2 statement) If you can prove me wrong feel free... I'd like to see proof that the CPU's core has such a high demand for memory bandwidth that there's no point of diminishing returns.

Are you difficient??? Do you even know what a bus does??? Putting it in the most simple terms.....faster bus = faster data transfer between CPU and memory = faster system performance (only if the memory is up to speed as well).

 

[WarCon]

Need for memory bandwidth is decided by software and or application. Example: High memory bandwidth is what makes the P4 excel in video and audio encoding. Otherwise, the processors efficiency (instructions per cycle) and speed (actual mhz) is more of a deciding factor in how fast an application runs.

 

[NightTrain]

Originally posted by: Jeff7181
NightTrain, thanks for the info and explanation rather than just saying "this is how it is, accept it"

But still, nobody answered my question... and I highly doubt that running the CPU core frequency and bus frequency in sync is going to be better than running the bus frequency at half the core frequency. (my 1500x2 and 3000x2 statement) If you can prove me wrong feel free... I'd like to see proof that the CPU's core has such a high demand for memory bandwidth that there's no point of diminishing returns.

I don't think anyone would argue that it's a linear progression. It's like a shopping mall...you need to get the most people in and out and you also need to sell them something. If any of those 3 break down, you get a bottleneck. It would seem logical to me that if all are working in perfect harmony, you get the most $$$

 

[Lonyo]

OK, here's a (the?) story:

The P4 architecture eats bandwidth for breakfast, lunch and dinner. It loves it, it can't get enough of it, it sucks it up and swallows it as much as it can.
The P4 isn't the Athlon, it doesn't get saturated in the same way.
With a P4, more bandwidth offered by higher FSB is very helpful to the processor, and there might be an upper limit, but it would be pretty damned high.
So higher FSB helps the P4 more than it would an Athlon because it offers more bandwidth, and the P4 can make use of that extra information, whereas the Athlon hits a limit fairly soon.

The 800MHz fact means although it's only 200MHz quad pumped, that still really gives the processor 800MHz, so it's a huge advantage. The 200MHz actual fact is a slightly moot point, except in terms of the RAM speed, which wouldn't always be 200MHz anyway because you might use a different divider to 1/1.
800MHz is 50% more than 533MHz, meaning the processor can recieve much more information, so it gives a big increase when the processor can handle that extra info.

 

[Wurrmm]

Right on the money dude.

 

[Jeff7181]

800MHz is 50% more than 533MHz, meaning the processor can recieve much more information, so it gives a big increase when the processor can handle that extra info.

That's nifty... but preliminary benchmarks show a maximum of a 12% gain in performance. Not exactly what I would expect from a 50% increase in bandwidth in a system that demands bandwidth.

 

[Jeff7181]

Originally posted by: Wurrmm

Are you difficient??? Do you even know what a bus does??? Putting it in the most simple terms.....faster bus = faster data transfer between CPU and memory = faster system performance (only if the memory is up to speed as well).

Don't be a prick. Keep your insults to yourself. You're doing nothing for "your side of the argument" by demonstrating your lack of knowledge by presenting information not backed up by facts or at least reasoning.

 

[Regs]

I agree with Jeff. It takes more than a cpu to increase the bus speed of the entire machine. You have a cpu requesting data from the ram at the rate of 800 Mhz, but the ram bus is only 400 Mhz, so the FSB is not really 800 Mhz. If you think about it, its maybe a 5% increase in performance over the 400 FSB intel .

 

[Jeff7181]

By the way... if someone is able to explain how the quad pumping works, please do... I understand that with DDR data is transmitted on the rising and falling side of the clock cycle... is it just transmitted twice on each side with the quad pumped bus?

 

[chsh1ca]

Originally posted by: Wurrmm
Are you difficient??? Do you even know what a bus does??? Putting it in the most simple terms.....faster bus = faster data transfer between CPU and memory = faster system performance (only if the memory is up to speed as well).

Well, using that formula, the Opteron shouldn't do anywhere near as well as it does, after all, its architecture is such that there is no real quantifiable 'FSB' in the sense of how the Athlon XP and the P4 works.
The major factor in small memory access situations is latency. It may be great that the P4 can pull lots of big data all at once, but when it has to access small amounts of data, it takes longer to get from point A to point B than an Athlon XP, which in turn is much longer than the Opteron. This is principally why many server operations favour low-latency memory systems to high-latency memory systems. On a webserver where you have a million chunks of data in 1KB segments, the Athlon XP would beat out a higher-clocked P4 in crunch time (as we've seen). Conversely, if you had a webserver with a single 1MB chunk of data, the P4 would likely access it much faster than the Athlon XP. The number may need to be bigger to create any kind of noticeable performance difference, but the example stands.

Your dangerously simple math of faster FSB = faster data transfer between CPU and memory = faster overall system performance also fails to address things like drive access speed, bus width, PCI bus I/O, and so forth. Theoretically, if you had a 128bit DDR400 memory system, it can transfer just as much data just as fast as the P4's 64bit 4x200MHz system. Maybe that's the next step, rather than jack up the electrical speed of the ram, just widen the bus until it becomes as effective. I wonder how much overhead that would add to manufacturing.

 

[RaynorWolfcastle]

Originally posted by: chsh1ca

Originally posted by: Wurrmm
Are you difficient??? Do you even know what a bus does??? Putting it in the most simple terms.....faster bus = faster data transfer between CPU and memory = faster system performance (only if the memory is up to speed as well).

Well, using that formula, the Opteron shouldn't do anywhere near as well as it does, after all, its architecture is such that there is no real quantifiable 'FSB' in the sense of how the Athlon XP and the P4 works.
The major factor in small memory access situations is latency. It may be great that the P4 can pull lots of big data all at once, but when it has to access small amounts of data, it takes longer to get from point A to point B than an Athlon XP, which in turn is much longer than the Opteron. This is principally why many server operations favour low-latency memory systems to high-latency memory systems. On a webserver where you have a million chunks of data in 1KB segments, the Athlon XP would beat out a higher-clocked P4 in crunch time (as we've seen). Conversely, if you had a webserver with a single 1MB chunk of data, the P4 would likely access it much faster than the Athlon XP. The number may need to be bigger to create any kind of noticeable performance difference, but the example stands.

Your dangerously simple math of faster FSB = faster data transfer between CPU and memory = faster overall system performance also fails to address things like drive access speed, bus width, PCI bus I/O, and so forth. Theoretically, if you had a 128bit DDR400 memory system, it can transfer just as much data just as fast as the P4's 64bit 4x200MHz system. Maybe that's the next step, rather than jack up the electrical speed of the ram, just widen the bus until it becomes as effective. I wonder how much overhead that would add to manufacturing.

You're missing the point entirely: the point is given the same architecture, more FSB bandwidth = more speed until you no longer need a dividing ratio (i.e. FSB and CPU are sync'ed) like in the good ol' days. Of course, this is assuming all other things are kept the same

 

[Jeff7181]

Sounds like Intel would benefit greatly by using an on-chip memory controller like AMD has done with the Opteron.

 

[Jeff7181]

Originally posted by: Wurrmm

Are you difficient??? Do you even know what a bus does??? Putting it in the most simple terms.....faster bus = faster data transfer between CPU and memory = faster system performance (only if the memory is up to speed as well).

Oh, and by the way... it's spelled "deficient"

 

[mroleg]

lmao jeff

 

[Jeff7181]

Originally posted by: mroleg
lmao jeff

I can play nasty too

 

[RaynorWolfcastle]

Originally posted by: Jeff7181
Sounds like Intel would benefit greatly by using an on-chip memory controller like AMD has done with the Opteron.

Doing that has pro's and cons, I'm sure Intel's looked into it.

The pro is that you greatly reduce latency since you no longer have to go through the chipset to access memory.

On the flip side, it means that you can't upgrade memory without upgrading the CPU. For the company this also means that they need to pdate the CPU very frequently to keep up with changes in RAM.

I guess Intel's strategy right now is to have gobs of memory bandwidth and try to hide the higher latencies they have by aggressively using data prefetching.

 

[NightTrain]

Originally posted by: Jeff7181
By the way... if someone is able to explain how the quad pumping works, please do... I understand that with DDR data is transmitted on the rising and falling side of the clock cycle... is it just transmitted twice on each side with the quad pumped bus?

From the same article:

"Addresses are sent twice per clock, which makes the FSB transfer addresses as fast as a 200/266MHz FSB would; and finally we have the quad-pumped data transfer rates, which means that data can be sent 4x per clock, effectively making the FSB transfer data as fast as a 400/533MHz FSB would. Since data, not address, transmission is what eats up the majority of FSB bandwidth, Intel gets away with calling the Pentium 4's FSB a 400/533MHz FSB."

 

[Jeff7181]

So does that mean data is transmitted twice on the rising side and twice on the falling side?

 

[NightTrain]

Originally posted by: chsh1caTheoretically, if you had a 128bit DDR400 memory system, it can transfer just as much data just as fast as the P4's 64bit 4x200MHz system.

Seems like I read something on Tom's about a single-channel DDR333 setup beating a dual-channel 266 in some instances.