Question 7nm I/O die ready, what about GlobalFoundries?

[Kedas]

Since the mobile APU design is a single die on 7nm, this means the 7nm I/O die design is basically ready.

If that is the case AMD will have no new products anymore that are using GlobalFoundries.
That would be strange unless they expect making old CPUs for a long time.

So do you think they change the I/O die to 7nm for the next products or will they keep hanging on the GlobalFoundries orders?

 

[RetroZombie]

With renoir assuming still having pcie3.0 integrated and the XBOX X also having pcie3.0 ssd and the sony ps5 having pcie4.0 ssd, how is it possible amd having so many ip ready for different products, who they borrow or collaborate to do the things?

 

[LightningZ71]

While it certainly makes sense that AMD would use N7 for an IO die for future EPYC and Threadripper, I wonder if it wouldn't be more economical and perhaps thermally beneficial to instead use a different process. TSMC has a couple of mature 10nm nodes that saw and still see a lot of volume in the mobile space. They are both denser and more energy efficient than GF 12nm, which will be an improvement. Given what AMD has publicly saidabout IO not scaling well with shrinks, a modest shrink that's focused on energy efficiency won't be too bad of a decision.

I do realize that AMD doesn't have a design that is setup for that node, but I can't imagine that TSMC can't help with that, nor would AMD make their designs so tailored that it would be completely impossible to transition the design to a different node.

 

[NTMBK]

While it certainly makes sense that AMD would use N7 for an IO die for future EPYC and Threadripper, I wonder if it wouldn't be more economical and perhaps thermally beneficial to instead use a different process. TSMC has a couple of mature 10nm nodes that saw and still see a lot of volume in the mobile space. They are both denser and more energy efficient than GF 12nm, which will be an improvement. Given what AMD has publicly saidabout IO not scaling well with shrinks, a modest shrink that's focused on energy efficiency won't be too bad of a decision.

I do realize that AMD doesn't have a design that is setup for that node, but I can't imagine that TSMC can't help with that, nor would AMD make their designs so tailored that it would be completely impossible to transition the design to a different node.

Or there's always FDSOI!

 

[NostaSeronx]

GlobalFoundries 7nm FDSOI should be in risk production when 12nm FDSOI is mid-volume ramp. 3rd Node for GlobalFoundries to use SOITEC's Smartcut 2.0 SOI wafers (NG-22FDX, 12FDX, 7FDX). 12FDX will not launch till smartcut 2.0 is feasible.

Smart Cut 1.0 wafers (more expensive) => Gate First FDSOI transistor stack (cheaper to implement)
Smart Cut 2.0 wafers (less expensive) => Gate Last FDSOI transistor stack (more expensive to implement)
As far as I can find from GloFo's EU projects.

 

[moinmoin]

With renoir assuming still having pcie3.0 integrated and the XBOX X also having pcie3.0 ssd and the sony ps5 having pcie4.0 ssd, how is it possible amd having so many ip ready for different products, who they borrow or collaborate to do the things?

Modularized design, allowing them to mix and match IP blocks. AMD's GPUs did that all the time already (GCN lived as long as it did since different IP blocks were gradually updated and improved over the years), and the semi custom business built upon that capability. With Zen and IF AMD is finally starting to apply this to their CPUs as well.

 

[Ajay]

Or there's always FDSOI!

Missing '/sarcasm' tab ??

 

[RetroZombie]

Modularized design, allowing them to mix and match IP blocks

Thanks for the reply!
But do you think it's their ip on the sony and microsoft console, or is sony ip on ps5 or someone else ip?
It's impressive what they have already done at 7nm, the amount of 'stuff'.

I'm just asking this because if it's their ip we could see some second apu release this year* with zen2 + rdna2 just like the consoles.

*If the virus allows it.

 

[moinmoin]

But do you think it's their ip on the sony and microsoft console, or is sony ip on ps5 or someone else ip?

It's a mix of everything.

Like AMD used a licensed IMC for Zen and Zen+ and (afaik) its own IMC in Zen 2. We know Sony has dedicated silicon area for audio processing in PS5 (called Tempest 3D), which uses a modified GPU compute unit. The modification would be Sony's IP, built upon AMD's IP. We also know that the embedded Zen chips support up to 4x 10GbE per die, which is apparently licensed. Since the dies are the same used for the mobile, desktop and server market the unused IP is disabled there. AMD specifically advertises its semi custom business as a way to allow combining AMD's IPs and development knowledge with one's own or other licensable IPs.

Unfortunately it's not publicly documented which IPs are licensed in a given product so the extend of it is anyone's guess.

 

[Atari2600]

While it certainly makes sense that AMD would use N7 for an IO die for future EPYC and Threadripper, I wonder if it wouldn't be more economical and perhaps thermally beneficial to instead use a different process. TSMC has a couple of mature 10nm nodes that saw and still see a lot of volume in the mobile space. They are both denser and more energy efficient than GF 12nm, which will be an improvement. Given what AMD has publicly saidabout IO not scaling well with shrinks, a modest shrink that's focused on energy efficiency won't be too bad of a decision.

We probably need to be careful about not applying the maxim "IO doesn't scale well" blindly - especially if we then extrapolate that to "the IO chip will never scale well".

While its obvious that the pads can never scale as well as a transistor, a clever floor plan could work around that.

For instance, if AMD ever decided to put L4 cache in the IO chip that equation of scaling vs. return would instantly be changed, if not turned upside down.

 

[RetroZombie]

IO doesn't scale well

I'm not sure if that is the problem. One of the problems would be the cost of the manufacturing process, why use such advanced process in something that doesn't need it and isn't cheap.

A good example would be the imc and the pcie, ddr4 imc done at 28nm or 14nm or 7nm all will still be ddr4 imc and all have to be running on jedec spec (2933Mhz for example), of course the one done at 7nm will always be smaller and more power efficient, but the technical specifications of the imc kept the same. The same goes for the other parts pcie, usb, ...