65nm

[Viditor]

First, I'm writing this to generate some good debate...but please try to limit the Intel/AMD rocks/sucks comments...

This is my opinion based on known facts. Contrary opinions are most welcome!

1. I have seen many posts recently that are of the opinion that 65nm will cut the costs of the upcoming Intel CPUs. However, in order to increase the performance of those chips, Intel is also doubling it's cache size. Since this will increase the overall footprint of the chip by ~60%, it seems to me that the cost in terms of chips/wafer for the 65nm chips will remain the same.
2. 65nm is a new process for Intel, hence it must go through a ramping process on it. This almost always means that early yields will be poor until the lines are properly tweaked. The net effect will be (IMHO) an actual increase in the cost of the chips for Intel.
3. AMD is currently producing 65nm parts but isn't releasing them according to Infoworld

I was quite taken by the capabilities of AMD?s new infrastructure. It not only churns out 100 million processors a year, it?s already producing 65-nanometer AMD microprocessors. No one outside AMD will ever see these, and Fab 36?s initial parts will be 90nm AMD64 processors

4. According to this article, they are using 10% of their line as an R&D testbed. They expect to begin production at already mature yields.

"As we go to 65 nm, our desire is to actually start production at mature yields. When we introduced 90 nm at very close to mature yields and were able to get it to mature yields very quickly, the expectation for people that run manufacturing now is that we will bring technologies in at mature yields"

My thoughts are that getting to 65nm first isn't and shouldn't be a "race" because Intel and AMD have entirely different motivations for doing so.
For Intel, it's necessary to move quickly from a performance perspective.
For AMD, it's necessary to do so only when it will show a net profit and when they can begin their production already ramped to mature yields...

Comments?

 

[Hacp]

ummmm. I thought that northwoods were equal to prescotts in terms of cost for cpus were they not???

 

[Viditor]

Originally posted by: Hacp
ummmm. I thought that northwoods were equal to prescotts in terms of cost for cpus were they not???

A fair point...I don't believe that Intel's costs were the same (meaning that they cut their profit on Prescotts for marketing reasons). But you bring up a valid point as far as what they will cost us. The only difference I see there is that the initial Prescotts didn't perform as well as the Northwoods they were replacing, so charging more would have dug pretty deep into Intel's sales.

Edit: That reminds me...IIRC, the prescotts weren't available (for the most part) during the first 5-6 months of their release. I seem to remember Dell kicking up quite a fuss about it...

 

[Markfw]

I think your logic is impeccable ! AMD did it right on 90nm and Intel didn't (a fact) and I think we are looking at another of the same. AMD can't affort to spend a lot of money fixing problems, they are poor compared to Intel. Their logic is good, and has proven correct.

Then again, Intel may have learned from their 90nm mistake, so I will leave final judgement until they both are at 65nm production !

 

[Accord99]

Originally posted by: Viditor
1. I have seen many posts recently that are of the opinion that 65nm will cut the costs of the upcoming Intel CPUs. However, in order to increase the performance of those chips, Intel is also doubling it's cache size. Since this will increase the overall footprint of the chip by ~60%, it seems to me that the cost in terms of chips/wafer for the 65nm chips will remain the same.

Increasing the L2 cache of Prescott from 1MB to 2MB only increased the die size by 20%. Cedar Mill should be roughly 70mm^2. Yonah is only slightly larger than Dothan at about 90mm^2.

 

[Viditor]

Originally posted by: Markfw900
I think your logic is impeccable ! AMD did it right on 90nm and Intel didn't (a fact) and I think we are looking at another of the same. AMD can't affort to spend a lot of money fixing problems, they are poor compared to Intel. Their logic is good, and has proven correct.

Then again, Intel may have learned from their 90nm mistake, so I will leave final judgement until they both are at 65nm production !

Thanks Mark...
One point though, Intel didn't really have a choice about pushing into 90nm ASAP. If you'll recall, they had hit a very unexpected wall on clockspeed. Without 90nm, they couldn't produce ANY new processors (good or bad). Where (in hindsight) they made the biggest mistake was in discontinuing the Yamhill project and going with Netburst. It's easy to see that now, but maybe Intel will have learned a valuable lesson from it...NEVER LET MARKETING DECIDE YOUR ENGINEERING!

 

[Viditor]

Originally posted by: Accord99

Increasing the L2 cache of Prescott from 1MB to 2MB only increased the die size by 20%. Cedar Mill should be roughly 70mm^2. Yonah is only slightly larger than Dothan at about 90mm^2.

?
If you look at an actual die picture, you'll see that 2MB of cache is about 60% of the whole die. Doubling that to 4MB is an increase of 2/3...

 

[Zebo]

You're smarter than me so I'll defer.. Lemme just say Intels new chips look pretty exciting from anands preview. I want to see a 4.5 vs 3.0Ghz shootout.. That will be fun. Couple $150 chips like Pentium 631 and Opteron 144 OCed to the MAX. Cheap high levels of goodness.

 

[Viditor]

You're smarter than me so I'll defer..

Doubtful...you probably have a life, that's all. What's it like?

 

[Zebo]

LOL well processes and profit just never intrested me but I beleive everything you said. I like end product and numbers it throws as the consumer.

 

[dmens]

Intel does not need to move to 65nm because of performance. Cedarmill is not a performance product, but moving sooner to 65nm will help future 65nm releases. That is the main reason for moving quickly. Also, 65nm isn't new for Intel, it has been around for quite some time.

IMO it is not wise to wait for a process to fully mature before moving to it, because an early move will give vaulable silicon experience and allow more robust steppings to be pulled in the schedule. The 90nm move by Intel was often viewed as a process failure, but it wasn't (again imo).

 

[Accord99]

Originally posted by: Viditor
?
If you look at an actual die picture, you'll see that 2MB of cache is about 60% of the whole die. Doubling that to 4MB is an increase of 2/3...

That's AMD. Intel has much better cache density.

http://www.techreport.com/reviews/2005q1/pentium4-600/index.x?pg=1

 

[Viditor]

Originally posted by: Accord99

Originally posted by: Viditor
?
If you look at an actual die picture, you'll see that 2MB of cache is about 60% of the whole die. Doubling that to 4MB is an increase of 2/3...

That's AMD. Intel has much better cache density.

http://www.techreport.com/reviews/2005q1/pentium4-600/index.x?pg=1

Good catch Accord, thanks!
So it appears that the cache (from the jpg) is ~40% of the die, then CedarMill should be ~94.5 mm2 (135 mm2 + 54mm2 for cache divide by 2 for 65nm).

 

[Accord99]

135mm^2 should be the total size of the entire Prescott-2MB die.

 

[coldpower27]

Originally posted by: Viditor
First, I'm writing this to generate some good debate...but please try to limit the Intel/AMD rocks/sucks comments...

This is my opinion based on known facts. Contrary opinions are most welcome!

1. I have seen many posts recently that are of the opinion that 65nm will cut the costs of the upcoming Intel CPUs. However, in order to increase the performance of those chips, Intel is also doubling it's cache size. Since this will increase the overall footprint of the chip by ~60%, it seems to me that the cost in terms of chips/wafer for the 65nm chips will remain the same.
2. 65nm is a new process for Intel, hence it must go through a ramping process on it. This almost always means that early yields will be poor until the lines are properly tweaked. The net effect will be (IMHO) an actual increase in the cost of the chips for Intel.
3. AMD is currently producing 65nm parts but isn't releasing them according to Infoworld

I was quite taken by the capabilities of AMD?s new infrastructure. It not only churns out 100 million processors a year, it?s already producing 65-nanometer AMD microprocessors. No one outside AMD will ever see these, and Fab 36?s initial parts will be 90nm AMD64 processors

4. According to this article, they are using 10% of their line as an R&D testbed. They expect to begin production at already mature yields.

"As we go to 65 nm, our desire is to actually start production at mature yields. When we introduced 90 nm at very close to mature yields and were able to get it to mature yields very quickly, the expectation for people that run manufacturing now is that we will bring technologies in at mature yields"

My thoughts are that getting to 65nm first isn't and shouldn't be a "race" because Intel and AMD have entirely different motivations for doing so.
For Intel, it's necessary to move quickly from a performance perspective.
For AMD, it's necessary to do so only when it will show a net profit and when they can begin their production already ramped to mature yields...

Comments?

It is unlikely that yields at 65nm are poor, as indications so far have pointed to it being a step up from 90nm, with reduced power conumsption, even with the poor example of NetBurst Architecture.

Cedar Mill is going to be somewhere in the ball park of 78mm2 as that is around 60% of the current Prescott-2M 135mm2 die size.

Intel isn't using the 65nm for performance at the get go, it using for reduced power cosumption, and more dies per wafer, plus economical production of Dual Core products. Intel will use the new process for performance later on in 2006 when Conroe and Merom arrive.

Also if you use Willamette 217mm2 to Northwood 146mm2 shrink as an indicator of how things will come for the Prescott-1M 112 to Cedar Mill 75mm2 shrink you can see that 75-80mm2 for Cedar Mill is in the right ball park.

 

[coldpower27]

Originally posted by: dmens
Intel does not need to move to 65nm because of performance. Cedarmill is not a performance product, but moving sooner to 65nm will help future 65nm releases. That is the main reason for moving quickly. Also, 65nm isn't new for Intel, it has been around for quite some time.

IMO it is not wise to wait for a process to fully mature before moving to it, because an early move will give vaulable silicon experience and allow more robust steppings to be pulled in the schedule. The 90nm move by Intel was often viewed as a process failure, but it wasn't (again imo).

No it wasn't, 90nm process seemed like a failure only because of the NetBurst products produced on it, there weren't any problems with the Pentium M's and chipsets that were produced on the very same process, the heat and leakage problems are related to NetBurst Architecture itself and it's dependence on high clockspeeds, and not quite so much on the process itself.

 

[coldpower27]

Originally posted by: Hacp
ummmm. I thought that northwoods were equal to prescotts in terms of cost for cpus were they not???

Not production wise, as they allowed more proessors from the same wafer, they only sold the processor for the exact same price of Northwood equivalent to help speed the transistion to Prescott based processor over the more expensive to make Northwood and simply pocket the additional money saved, and get addtional profits.

 

[Viditor]

Originally posted by: coldpower27
It is unlikely that yields at 65nm are poor, as indications so far have pointed to it being a step up from 90nm, with reduced power conumsption, even with the poor example of NetBurst Architecture.

Cedar Mill is going to be somewhere in the ball park of 78mm2 as that is around 60% of the current Prescott-2M 135mm2 die size.

Intel isn't using the 65nm for performance at the get go, it using for reduced power cosumption, and more dies per wafer, plus economical production of Dual Core products. Intel will use the new process for performance later on in 2006 when Conroe and Merom arrive.

Also if you use Willamette 217mm2 to Northwood 146mm2 shrink as an indicator of how things will come for the Prescott-1M 112 to Cedar Mill 75mm2 shrink you can see that 75-80mm2 for Cedar Mill is in the right ball park.

I agree with you and Accord on Cedarmill's die size...I was having a brain fart and do apologise.
On the yields however I have to disagree. If past Intel ramps are any indication, I don't expect decent yields on 65nm for at least 6 months into the ramp. Let me be clear that I expect them to eventually get the yields up to some good levels, but certainly not at the beginning...
As to performance needs, am I incorrect that Intel is releasing 2MB/core Pressler almost immediately? I thought it was also slated for Q1 06...
If they aren't, it seems almost silly to release it at all...unless there is a slip on Conroe's release.

 

[dmens]

Originally posted by: Viditor
If past Intel ramps are any indication, I don't expect decent yields on 65nm for at least 6 months into the ramp.

Not ramps, there was just one bad (1262). And the reason that didn't turn out well was not the process, it was prescott. And from what I hear, the 65nm process is ramping up right now with early Cedarmill steps. People have worked very hard to avoid the mistakes of 90nm.

 

[Viditor]

Originally posted by: dmens
Intel does not need to move to 65nm because of performance. Cedarmill is not a performance product, but moving sooner to 65nm will help future 65nm releases. That is the main reason for moving quickly. Also, 65nm isn't new for Intel, it has been around for quite some time.

IMO it is not wise to wait for a process to fully mature before moving to it, because an early move will give vaulable silicon experience and allow more robust steppings to be pulled in the schedule. The 90nm move by Intel was often viewed as a process failure, but it wasn't (again imo).

I don't think Intel has ever had production level 65nm before, but please let me know if you can find an example...
As to waiting on the 65nm ramp, again this is where AMD and Intel differ. They don't approach manufacturing the same...
Intel uses "copy everything" manufacturing, which makes perfect sense for them as they have so many Fabs. It would not be in Intel's best interest to wait until maturity.
AMD uses their APM system, which makes perfect sense for them as they require their 1 or 2 Fabs to make adjustments VERY quickly, even at the level of individual wafers!
The upshot is that AMD is far more efficient for mid to low scale manufacturing, and Intel is more efficient for very large scale manufacturing.
AMD probably has a MUCH faster ramp speed than Intel, but they cannot match Intel's huge volume...

 

[Viditor]

Originally posted by: dmens

Originally posted by: Viditor
If past Intel ramps are any indication, I don't expect decent yields on 65nm for at least 6 months into the ramp.

Not ramps, there was just one bad (1262). And the reason that didn't turn out well was not the process, it was prescott. And from what I hear, the 65nm process is ramping up right now with early Cedarmill steps. People have worked very hard to avoid the mistakes of 90nm.

I had guessed that, but many thanks for the confirming info!! I won't embarass you by asking if you know what yields they're getting (of course if you want to message me...)
But we have one turn left before launch, so I would hope that Cedarmill is already ramping and going into inventory (I really don't think another paper launch would fly at this point...)

 

[frostedflakes]

Originally posted by: coldpower27

Originally posted by: dmens
Intel does not need to move to 65nm because of performance. Cedarmill is not a performance product, but moving sooner to 65nm will help future 65nm releases. That is the main reason for moving quickly. Also, 65nm isn't new for Intel, it has been around for quite some time.

IMO it is not wise to wait for a process to fully mature before moving to it, because an early move will give vaulable silicon experience and allow more robust steppings to be pulled in the schedule. The 90nm move by Intel was often viewed as a process failure, but it wasn't (again imo).

No it wasn't, 90nm process seemed like a failure only because of the NetBurst products produced on it, there weren't any problems with the Pentium M's and chipsets that were produced on the very same process, the heat and leakage problems are related to NetBurst Architecture itself and it's dependence on high clockspeeds, and not quite so much on the process itself.

Exactly. Prescott's problem wasn't the shrink to 90nm, it was the fact that it had a 33% longer pipeline than Northwood (31 stages with Prescott vs. 21 with Northwood). This should be very obvious, as Pentium-M/P6 and AMD K8 (short-pipe architectures) made a very smooth and successful transition to 90nm.

 

[Viditor]

Originally posted by: frostedflakes
Exactly. Prescott's problem wasn't the shrink to 90nm, it was the fact that it had a 33% longer pipeline than Northwood (31 stages with Prescott vs. 21 with Northwood). This should be very obvious, as Pentium-M/P6 and AMD K8 (short-pipe architectures) made a very smooth and successful transition to 90nm.

Actually, the 90nm move had a big problem in manufacturing as well...dmens is saying (I think) that it can be attributed mainly to the design of Prescott, but Intel was getting HORRIBLE yields at the start, and they weren't able to produce much quantity at all for the first 6 months...

 

[stevty2889]

Part of the main problem with Intels 90nm was the design changes done to Prescott, which ended up causing heat issues, and it never reached the potential it was intended for. Dothan, which run on the same process, didn't have such drastic changes over Banias, so it was a much smoother transition. The first 65nm chips, are die shrunk prescotts, with no real changes, so it seems it will be much less of a problem, and they will get the normal benifits from the shrink. Not sure where you are getting the double cache from, because cedar mill has 2mb of cache just like the 6xx series prescotts, and presler is comparible to a dual core with 2 6xx type chips, rather than 5xx chips like smithfield, so nothing major there, so the overall die size is still smaller. The transiton to 65nm isn't likely going to have any of the problems the transition to 90nm did, so everything should be released on schedule.

Perfomance wise however, these netburst chips won't have any performance gains over the 90nm parts, because there were no changes done. The 2mb of cache the 6xx series got didn't have any major performance increase, so Presler won't likely get much boost from the extra cache, it's advantage is the slightly reduced power and heat allows for slightly higher clock speeds.

 

[coldpower27]

Originally posted by: stevty2889
Part of the main problem with Intels 90nm was the design changes done to Prescott, which ended up causing heat issues, and it never reached the potential it was intended for. Dothan, which run on the same process, didn't have such drastic changes over Banias, so it was a much smoother transition. The first 65nm chips, are die shrunk prescotts, with no real changes, so it seems it will be much less of a problem, and they will get the normal benifits from the shrink. Not sure where you are getting the double cache from, because cedar mill has 2mb of cache just like the 6xx series prescotts, and presler is comparible to a dual core with 2 6xx type chips, rather than 5xx chips like smithfield, so nothing major there, so the overall die size is still smaller. The transiton to 65nm isn't likely going to have any of the problems the transition to 90nm did, so everything should be released on schedule.

Perfomance wise however, these netburst chips won't have any performance gains over the 90nm parts, because there were no changes done. The 2mb of cache the 6xx series got didn't have any major performance increase, so Presler won't likely get much boost from the extra cache, it's advantage is the slightly reduced power and heat allows for slightly higher clock speeds.

Viditor tried, attributing that Presler was a large die compared to Smithfield, because instead of having 2 Prescott-1M slapped together, vs 2 Cedar Mills (2MB) slapped together. However I believe he was using AMD's cache densities as a yard stick, which is wrong for Intel's cache as they tend to be twice as dense as AMD's on a given process. However I believe we have established that 2 Cedar Mills aka Presler is still ~ 25% reduction in die size in comparison to Smithfield, even with the increased cache.