65nm

[coldpower27]

Originally posted by: Viditor

Originally posted by: frostedflakes
Exactly. Prescott's problem wasn't the shrink to 90nm, it was the fact that it had a 33% longer pipeline than Northwood (31 stages with Prescott vs. 21 with Northwood). This should be very obvious, as Pentium-M/P6 and AMD K8 (short-pipe architectures) made a very smooth and successful transition to 90nm.

Actually, the 90nm move had a big problem in manufacturing as well...dmens is saying (I think) that it can be attributed mainly to the design of Prescott, but Intel was getting HORRIBLE yields at the start, and they weren't able to produce much quantity at all for the first 6 months...

I disagree, I believe Intel just wasn't getting good yields on products 3.4GHZ and higher at the beginning, as they were having those heat and leakage issues, the lower speed bins 2.8GHZ - 3.2GHZ faired allright. Hence the intorudction of Northwood 3.4GHZ. From the pricing structure, Intel had good enough yield at the introduction of Prescott to simply charge identical pricing, in realation to Northwood, which signifies that Intel was in good shape to go selling the more mainstream products to displace the older cores.

 

[IntelUser2000]

Frostedflakes is right to point out the fact that indeed its not the 90nm process that's at fault for Prescott. Just look at Dothan. If any of you followed roadmaps for Pentium M back from Banias, you could see that Dothan was supposed to be 1.8GHz. It actually came at 2.0GHz, and at lower power.

Also there was an article at Inquirer saying that focus to Cedarmill/Presler has been shifted to Merom/Conroe, and there isn't much engineers working at Cedarmill/Presler to optimize the CPUs, for say power consumption and clock speeds. Mainly, the reason for 65nm I believe for Cedarmill/Presler is not power consumption, as indicated by only 20%reduction in power consumption. Its more likely that they don't have any alternatives until Merom/Conroe generation.

 

[IntelUser2000]

Intel's cache size in mm2 for 90nm Prescott's 1MB L2 is 16-17mm2. Smithfield has two of them, and total die size is 206mm2. That means L2 cache takes only 17% of die size. 4MB L2 would make total die size at 240. Ideally Presler should be EXACTLY half of that at 120mm2, but it doesn't happen, looking at Banias to Dothan transition, it was more like65%. From what I know, Presler's die size is looking to be little over 140mm2, and Cedarmill at 70mm2.

 

[Viditor]

Originally posted by: coldpower27

Originally posted by: Viditor

Originally posted by: frostedflakes
Exactly. Prescott's problem wasn't the shrink to 90nm, it was the fact that it had a 33% longer pipeline than Northwood (31 stages with Prescott vs. 21 with Northwood). This should be very obvious, as Pentium-M/P6 and AMD K8 (short-pipe architectures) made a very smooth and successful transition to 90nm.

Actually, the 90nm move had a big problem in manufacturing as well...dmens is saying (I think) that it can be attributed mainly to the design of Prescott, but Intel was getting HORRIBLE yields at the start, and they weren't able to produce much quantity at all for the first 6 months...

I disagree, I believe Intel just wasn't getting good yields on products 3.4GHZ and higher at the beginning, as they were having those heat and leakage issues, the lower speed bins 2.8GHZ - 3.2GHZ faired allright. Hence the intorudction of Northwood 3.4GHZ. From the pricing structure, Intel had good enough yield at the introduction of Prescott to simply charge identical pricing, in realation to Northwood, which signifies that Intel was in good shape to go selling the more mainstream products to displace the older cores.

Actually, in April of 2004, Dell stopped selling their systems with the 3.0, 3.2, and 3.4 GHz Prescotts, and reverted back to Northwood on all of them. They stated it was a supply issue from Intel on the Prescott processors.
Also, on the Dothan, it was delayed from January until May...

 

[Viditor]

Originally posted by: IntelUser2000
Intel's cache size in mm2 for 90nm Prescott's 1MB L2 is 16-17mm2. Smithfield has two of them, and total die size is 206mm2. That means L2 cache takes only 17% of die size. 4MB L2 would make total die size at 240. Ideally Presler should be EXACTLY half of that at 120mm2, but it doesn't happen, looking at Banias to Dothan transition, it was more like65%. From what I know, Presler's die size is looking to be little over 140mm2, and Cedarmill at 70mm2.

OK, and that seems to tally...
So the Manchester at 147mm2, or the Toledo at 199mm2 and a very mature manufacturing process will be competing against the Presler at 140mm2 with a brand new manufacturing process...

1. Whether you agree or disagree on Intel's need for performance enhancement, you must certainly agree that Intel needs to get 65nm out ASAP for the temp and power savings...
2. I imagine that those of you who know manufacturing will agree that AMD's mature 90nm process should be at least 20-30% more efficient on yields than Intel's brand new 65nm for at least the first 2-3 turns (6-9 months)
3. Since 199mm2 is ~30% larger than 140mm2, I submit that the actual COGS will be equivalent for Toledo, and much cheaper for Manchester.
4. If AMD's claims about APM are true, then they will be producing 65nm parts for shipping at fully mature yields about the same time that Intel is...

 

[GFORCE100]

Originally posted by: Markfw900
I think your logic is impeccable ! AMD did it right on 90nm and Intel didn't (a fact) and I think we are looking at another of the same. AMD can't affort to spend a lot of money fixing problems, they are poor compared to Intel. Their logic is good, and has proven correct.

Then again, Intel may have learned from their 90nm mistake, so I will leave final judgement until they both are at 65nm production !

There is a difference running a processor at max 2.8GHz and at 3.8GHz not to forget two of them on a dual core Pentium D. If AMD was clocking its chips that high (theoritcally speaking because the design won't allow it) then heat issues would also crop up.

 

[Furen]

Everything you pointed out will, most likely, lower Intel's gross margins on the 65nm parts (at least initially), but I doubt it will lead to shortages. Even if yields are horrible at first (it doesnt sound like they are, by the way), Intel has enough manufacturing capacity to basically throw money at the problem until yields reach satisfactory numbers. Efficiencymatters to AMD because it is so capacity constrained, so it has to make the most out of the little it has, while Intel is going to throw two 300mm Fabs at the 65nm process. 65nm parts should take about half the area as 90nm parts (Paxvilles) and the fact that Intel will use dual-die CPU packages instead of dual-core, single-die ones will help out yields tremendously.

The cost of goods sold, of course, is of no relevance to anyone who has no interest in Intel's finanacials (ie. the consumers). If analyzing Intel as an investor, I'd have to point out that though short-term profits will probably suffer a little, the long-term gains of accelerating the 65nm process will be huge. After all, Intel can't even think about introducing the merom/conroe families of CPUs until the 65nm is very mature. Prices on these 65nm CPUs will, most likely, be competitive, since Intel cant afford to alienate any OEMs (nor can it alienate consumers, either) by hiking the prices on 65nm parts too much.

Originally posted by: GFORCE100
There is a difference running a processor at max 2.8GHz and at 3.8GHz not to forget two of them on a dual core Pentium D. If AMD was clocking its chips that high (theoritcally speaking because the design won't allow it) then heat issues would also crop up.

Not quite, the processors are VERY different. If AMD built prescotts for Intel on the same process it builds A64s, the SOI process would lower their leakage quite a bit (I've seen 25% less leakage throw around but I'd take that with a grain of salt). The problem for Intel was the same as ATI's current problems. Intel made a brand new processor (the core was completely redesigned to add more pipeline stages, 64 bits, improved branch prediction, etc), it made it on a brand-new process (90nm) and it threw strained silicon on it, just for kicks. Having so many unknowns will almost invariably lead to problems. AMD, on the other hand, played it safe. It went for SOI before shrinking to 90nm (the hammers), then it went to 90nm (winchester), and finally did dual stress layer (venice). It allowed itself time to get confortable with one tech before jumping onto the next because it was capacity constrained to begin with and wouldn't have been able to survive horrible yields for as long as Intel did.

 

[Viditor]

Some good points Furen...one thing though, last January Intel posted some good numbers EXCEPT for their margins. At their conference call, they assured their investors and analysts that those margins would be back up to normal levels in a year.
If they take a hit in margins again anytime soon, they are going to erode confidence in the company more than it already has been. I don't think that they will do that, but you may be right...we shall have to wait and see.
Your point on them using 2 Fabs is also correct, but not at 100% (or so they've said). Also, those 2 Oregon Fabs are quite small by todays standards...

I think COGS is only important to the consumer if you believe that Intel must keep margins up. It means that they will probably not be introducing 65nm parts at low prices...
Intel may very well be caught between a rock and a hard place.

 

[Furen]

Very well, a Fab and a half (better?). Intel's overall profit margins are lowered by the low-end, low-margin parts. The 65nm parts are supposed to be higher-end parts, and they're supposed to stimulate demand for the high-end chips (I'm not sure if they'll accomplish this, but they might). Intel is already well in its way to raise its profit margins (by discontinuing low-margin parts, like low-end chipsets) so I wouldnt say that even if the profit margins on the INITIAL 65nm parts is lower, Intel's overall will be less than last year's. Then there's Yonah, which should be quite successful (not to mention smaller than 90n Dothans).

Higher prices on 65nm parts would also serve to curb demand on the parts, which, in turn, would make the supply a little less tight. Higher prices on the 65nm parts are a given, in my opinion, but I would not expect this premium to be too much.

 

[coldpower27]

Originally posted by: Furen
Very well, a Fab and a half (better?). Intel's overall profit margins are lowered by the low-end, low-margin parts. The 65nm parts are supposed to be higher-end parts, and they're supposed to stimulate demand for the high-end chips (I'm not sure if they'll accomplish this, but they might). Intel is already well in its way to raise its profit margins (by discontinuing low-margin parts, like low-end chipsets) so I wouldnt say that even if the profit margins on the INITIAL 65nm parts is lower, Intel's overall will be less than last year's. Then there's Yonah, which should be quite successful (not to mention smaller than 90n Dothans).

Higher prices on 65nm parts would also serve to curb demand on the parts, which, in turn, would make the supply a little less tight. Higher prices on the 65nm parts are a given, in my opinion, but I would not expect this premium to be too much.

Well I am not sure about this one, as both these Fab's look larger then AMD's own Fab 36. Both Fab D1D, & Fab 12 the two 65nm Fab slated for intial production, have over 200K Sq Feet of clean room space eahc mind you. In comparison AMD's Fab 36 only has 143 K Sq Feet. Though I believe there is room for improement on AMD's end, they left room for expandability.

 

[Accord99]

This post on realworldtech has some information on the size of Intel and AMD's fabs:

http://realworldtech.com/forums/index.c...3764&Thread=95&roomID=11&entryID=57274

 

[Markfw]

where is fab36 in that ? Looks like a crap post to me.

 

[Accord99]

He mistyped Fab32 for Fab 36. The information otherwise is accurate.

 

[Furen]

I don't understand why everyone keeps trying to compare AMD's capacity to Intel's. AMD is completely capacity-overmatched by Intel, it has been so since long ago and it will be so for a while yet (I dont think AMD will match Intel's capacity ever, but it could happen). But capacity really doesn't make a difference unless AMD is capacity constrained (which it was before, but shouldn't be now that FAB36 is starting up).

 

[Viditor]

Sorry, I misspoke...when I said size I should have said output.
I could certainly be wrong here, but IIRC, D1D only outputs 3000 wspw...
However, for the life of me I can't find confirmation either way. If someone could locate a link with the output data for Intel's Fabs, I would greatly appreciate it (it would help a lot with my models...).

Furen is absolutely correct..."size doesn't matter"!

 

[KeepItRed]

AMD > Intel

/thread

 

[IntelUser2000]

2. I imagine that those of you who know manufacturing will agree that AMD's mature 90nm process should be at least 20-30% more efficient on yields than Intel's brand new 65nm for at least the first 2-3 turns (6-9 months)

Actually, excluding your imagination, Intel has the highest yield for their process out of the whole semiconductor industry, and even against IBM, as IBM had issues with producing 130nm and 90nm PowerPC chips and admitted they lost money because of their process, while Intel didn't.

the SOI process would lower their leakage quite a bit (I've seen 25% less leakage throw around but I'd take that with a grain of salt).

Uh-huh. If you look at individual transistor comparisons(and actually bother to search for them, which I did), IBM/AMD's 65nm transistors have same performance as Intel's 65nm process while the comparison used had Intel's transistor at HALF the leakage of IBM/AMD.

Actually, in April of 2004, Dell stopped selling their systems with the 3.0, 3.2, and 3.4 GHz Prescotts, and reverted back to Northwood on all of them. They stated it was a supply issue from Intel on the Prescott processors.
Also, on the Dothan, it was delayed from January until May...

Err, excluding Prescott, let's look at Dothan.

The rumors for than were that it will be out at 1.8GHz top speed, and although it got delayed, it actually came as 2.0GHz for top speed.

Plus, there were rumors saying that it will consume much higher power than Banias due to 90nm process problems, but actually it came at LOWER POWER AND HIGHER CLOCK SPEED.

Reason for Dothan's delay right from ANANDTECH: http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2129

Intel has already publicly released the reason for Dothan's delay. There was apparently an analog design issue with Dothan; more specifically, a PLL was too jittery. Dothan was actually in the hands of OEMs back in January, but the yields were extremely low, thanks to the jittery PLL issue. The solution to the problem required another spin of the silicon, which takes a long time (even longer at 90nm) and resulted in Dothan's lengthy delay.

So basically what happened with is they had good process tech but had really crappy chip.

Bad driver on a good car doesn't make the bad driver suddenly drive well does it??

 

[IntelUser2000]

AMD is really over-matched in capacity for manufacturing but CPUs aren't the only ones Intel makes.

 

[IntelUser2000]

So basically what happened with is they had good process tech but had really crappy chip.

In case somebody misunderstood, I was talking about Prescott and its variants not Dothan, sorry for confusion.

Yonah's die size is 90.7mm2, and Dothan is 87mm2, looks like the reason that Pentium M chips have consistently similar die size even though its possible to be smaller is so thermal density isn't higher.

...it threw strained silicon on it, just for kicks.

The reason for Strained Silicon was for higher transistor performance at 90nm process, just like introducing copper at 130nm.