Info 64MB V-Cache on 5XXX Zen3 Average +15% in Games

[Kedas]

Well we know now how they will bridge the long wait to Zen4 on AM5 Q4 2022.
Production start for V-cache is end this year so too early for Zen4 so this is certainly coming to AM4.
+15% Lisa said is "like an entire architectural generation"

 

[DrMrLordX]

@LightningZ71

You're spot-on, Zen3d lets people keep AM4 alive a little longer without blowing money on a new platform.

@jpiniero

AMD can allow Zen3d and Zen4/Raphael to co-exist to fill different niches in the market. There's no reason for them to delay Zen4 that much, but there's plenty of reason for AMD to extend the life of AM4, especially if TSMC has a surplus of N6 wafers available at a lower price/wafer than what AMD was paying for N7 back in 2019.

Boeing is another thing entirely. They were a great engineering led firm destroyed when the incompetent beancounter management from McDonnell Douglas took over.

McDonnel Douglas == BK/Bob Swan?

 

[jpiniero]

AMD can allow Zen3d and Zen4/Raphael to co-exist to fill different niches in the market. There's no reason for them to delay Zen4 that much

Unless they don't have the chips available because Zen 4 got delayed because of rona-related problems and/or Genoa is taking them all.

 

[CakeMonster]

Do we all assume that added cache is ready for prime time with Zen4? It would be rather confusing for consumers if Zen3(D) outperformed Zen4 in certain workloads if it isn't.

 

[Hitman928]

Do we all assume that added cache is ready for prime time with Zen4? It would be rather confusing for consumers if Zen3(D) outperformed Zen4 in certain workloads if it isn't.

5nm on 5nm stacking is supposed to be ready by 4Q2022 which is when Zen 4 is rumored to launch (AMD has confirmed 2022 but not which quarter).

 

[moinmoin]

So that mean rendered producible, wich they can not do with Zen 4 since they have no definitive silicon.

Zen 4? Did you lose your thread? You asked what productized means in a reply to this post:

• This technology will be productized with 7nm Zen 3-based Ryzen processors

The translation for you: V-Cache will be turned into a product using 7nm Zen 3-based Ryzen processors. No Zen 4 there.

 

[DisEnchantment]

I don't know the full cost of adding 1 stack of cache but I have an idea due to personal experience. Without full knowledge of all the costs and the yield AMD expects from stacking as well as taking hints from what AMD has revealed, I can only say that I don't have much confidence in AMD going 4+ hi stacks on Ryen 3d due to both costs of doing so and diminishing returns in performance. I do know that AMD knows these costs and if they think it is worth it from a cost and opportunity cost perspective, then we'll see those SKUs and I'll be happy to be wrong.

The answer was already given, so no need to guess. Pretty much what you and most people surmised.

In a call with AMD, we have confirmed the following:

• The V-Cache is a single 64 MB die, and is relatively denser than the normal L3 because it uses SRAM-optimized libraries of TSMC's 7nm process, AMD knows that TSMC can do multiple stacked dies, however AMD is only talking about a 1-High stack at this time which it will bring to market.

AnandTech Forums: Technology, Hardware, Software, and Deals

Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

www.anandtech.com

 

[DisEnchantment]

There's no reason for them to delay Zen4 that much, but there's plenty of reason for AMD to extend the life of AM4, especially if TSMC has a surplus of N6 wafers available at a lower price/wafer than what AMD was paying for N7 back in 2019.

Surplus N6/N7 is a unicorn 😀 .
AMD's customers cannot get enough chips. Sony and MS already publicly said many time they are supply constrained all the way into end of 2022.
And official TSMC Foundry update said they will not invest anymore in N7/N6 capacity. The focus is N5 ramp.

 

[Mopetar]

Marketing demands new products. You can't go two full years without a product refresh. If Zen 3D launches at CES it could be 10-12 months before Zen 4 consumer does.

Why delay Zen 4 at all though? Or rather why would you not expect it until late 2022 or even 2023? That makes for an incredibly odd schedule on AMD's part.

I doubt Zen 3D is meant to be a top to bottom replacement for the whole line. I think AMD is just using it to help learn how to work with the technology that TSMC has so it can be more widely incorporated into future products.

Maybe it gets a limited release as a top-end Ryzen product, but it's far more valuable in Threadripper or Epyc.

 

[DrMrLordX]

Unless they don't have the chips available because Zen 4 got delayed because of rona-related problems and/or Genoa is taking them all.

Too much is being made of covid-19's effect on product launches. Availability of key components for motherboards? Maybe. As for Genoa, while I had suspected that it would receive top priority for all available N5 wafers sold to AMD, the fact remains that AMD can cobble together some early Raphael chips using CCDs ill-suited for Genoa.

Do we all assume that added cache is ready for prime time with Zen4? It would be rather confusing for consumers if Zen3(D) outperformed Zen4 in certain workloads if it isn't.

No. Zen4d would be impossible until Q4 2022 due to TSMC's packaging production schedule. Neither Genoa nor Raphael should feature stacked cache.

Surplus N6/N7 is a unicorn 😀 .

Maybe "surplus" is the wrong term to use here. The fact remains that many firms that were on TSMC N7 have moved on to other nodes, leaving a larger portion of wafers available to AMD. AMD will also move off N7/N6 eventually, at least for some products.

 

[Joe NYC]

On redundancy and yield — through-silicon-via (TSV) interconnects may also apply redundancy to improve yield:

BTW, I am wondering if one type of die can be configurable to be at any layer on stack or if each layer will need a different die...

 

[Joe NYC]

Why would anyone buy a Zen 3D mid-cycle when Zen 4 is that much closer? Particularly if details start to emerge suggesting that the next CPUs will use a new platform and that Zen 3D is a dead end platform wise.

From AMD POV, it is all about capacity that can be obtained from TSMC, and how it gets divided to products.

If Zen 3D can continue the run of AMD in Ryzen 3D and Milan 3D for 1 to 2 years, without taking any of the TSMC N5 capacity, then future growth can come from new N5 capacity without losing any N7 capacity due to being forced to migrate a product line from N7 to N5.

From POV of consumer, if Zen 3D is better than ADL and is cheaper, the dead end argument is weak. It means you have to overpay now and then pay again later to upgrade in order to beat Zen 3D. A dubious proposition.

 

[Joe NYC]

I think it is completely safe to expect that all future AMD's top of the line desktop/workstation CPUs will continue to ship with stacked L3. I have zero doubts that this 3D stacking will spread to other companies as well and AMDs GPU department too. It's like free lunch that also enables one to rise ASP and compete in market. We had clock wars, core count wars and now cache wars will properly begin.

Precisely. And for many types of applications, cache will add more than extra cores.

The future is bright overall, imagine Ampere, but instead of ridiculous 120W guzzling GDDR6X, it has 256MB of L3 stacked? I think this will give awesome one time performance boost to everyone from Nvidia to custom ARM crowd.

The race is on as far as how quickly vendors can get the V-Cache in their products.

And TSMC will have an easy way for next doubling of revenue- sell SRAM

My gut feeling about Z3D vs Alder Lake situation - for typical desktop and gaming ADL will be very handicapped by DDR5. Anandtech and other enthusiast serving sites will be happy to test it with DDR5 4800CL40 JEDEC, that will perform ~DDR4 2400CL20 levels and ~15-16ns of latency.
That is why we have Cinebench leak only - 30% IPC gain there, but probably disastrous performance everywhere else. Imagine Anandtech 11700K prerelease testing, but square it due to low speeds of new memory subsystem and immature IMC code.

I don't think the performance will be disastrous. I think the gaming ADL released in Q4 2021 will be better than Rocket Lake and better than current Zen 3.

So at stock speeds AMD will easily win with 96MB of L3, for proper enthusiasts a lot of things depend on prices and speeds of proper DDR5 memory ( and maybe DDR4 mobos?).

I think AMD will need some room for error, and secure ability to sell Zen 3D as highest performing product all through 2022.

 

[Joe NYC]

Do we all assume that added cache is ready for prime time with Zen4? It would be rather confusing for consumers if Zen3(D) outperformed Zen4 in certain workloads if it isn't.

I think Zen 4 will be release right out of the gate with some SKUs that will have 3D stacking.

My guess is that it will be even more optimized for stacking than Zen 3, perhaps with larger area on the die being low power, eligible for stacking, so that (together with slight reduction of SRAM cell in N5) the unit of stacking in Zen 4 goes up to 128MB.

 

[HurleyBird]

I think Zen 4 will be release right out of the gate with some SKUs that will have 3D stacking.

It's possible, but I don't think it will, at least not on mainstream desktops. Assuming Zen4 convincingly beats Alder Lake (a fair assumption, given that AMD apparently doesn't feel the need to release 24c Zen4), I see AMD holding back Zen4-3D until around the Meteor Lake timeframe. Among other things, they will be able to more aggressively bin those premium, cache-stacked stacked parts later on when the node is more mature.

 

[Joe NYC]

Surplus N6/N7 is a unicorn 😀 .
AMD's customers cannot get enough chips. Sony and MS already publicly said many time they are supply constrained all the way into end of 2022.
And official TSMC Foundry update said they will not invest anymore in N7/N6 capacity. The focus is N5 ramp.

AMD has been getting N7 capacity other customers have left behind voluntarily (Apple) or involuntarily (Chinese customers).

It's not clear if this can continue in the busier H2. Probably a slower pace of capacity growth for AMD.

 

[Joe NYC]

Why delay Zen 4 at all though? Or rather why would you not expect it until late 2022 or even 2023? That makes for an incredibly odd schedule on AMD's part.

I doubt Zen 3D is meant to be a top to bottom replacement for the whole line. I think AMD is just using it to help learn how to work with the technology that TSMC has so it can be more widely incorporated into future products.

Maybe it gets a limited release as a top-end Ryzen product, but it's far more valuable in Threadripper or Epyc.

Zen 4 delay - if there is a Zen 4 delay - will be most likely on the client side only and server Genoa launches without delay.

It may have something to do with competition.

If Zen 3D is superior to Alder Lake, Intel is screwed on client for another year +.

But on server, Intel will have Sapphire Rapids and Sapphire Rapids HBM in H1 2022 and H2 2022, which is going to be a more competitive part for Intel against Milan (X) than ADL would be for Zen 3D desktop.

 

[HurleyBird]

My guess is that it will be even more optimized for stacking than Zen 3, perhaps with larger area on the die being low power, eligible for stacking, so that (together with slight reduction of SRAM cell in N5) the unit of stacking in Zen 4 goes up to 128MB.

Two possibilities are stacked L2 and changing the L3 to be inclusive, although if one happens the other seems less likely by virtue of inclusive L3 making the most sense when L3 is relatively large vs L2.

 

[naukkis]

Two possibilities are stacked L2 and changing the L3 to be inclusive, although if one happens the other seems less likely by virtue of inclusive L3 making the most sense when L3 is relatively large vs L2.

It's a bit different than that. If made so that inclusive L2 is part of L3 L2 data isn't needed to be replicated in L3, so increasing L2 size won't duplicate anything, it actually guarantees that data which is located in L2 isn't duplicated in L3 data arrays. What it needs is that L3 has all sets that L2 does and AMD current implementation isn't made like that, different ways are split into different core's L3 basically making L2 as data inclusive part of L3 impossible( it's L2 is still tag inclusive in L3)

And that way parting data sets into different parts of L3 cache increases cache power efficiency over what is needed with data inclusive L3 Intel is also changed to it instead using inclusive L3. Also for read-optimized data sharing having data duplicated in L3 data arrays can also make things faster.

 

[yuri69]

It's possible, but I don't think it will, at least not on mainstream desktops. Assuming Zen4 convincingly beats Alder Lake (a fair assumption, given that AMD apparently doesn't feel the need to release 24c Zen4), I see AMD holding back Zen4-3D until around the Meteor Lake timeframe. Among other things, they will be able to more aggressively bin those premium, cache-stacked stacked parts later on when the node is more mature.

The problem for AMD is Alder Lake being a Q4 2021 product. They need to launch Zen 3D in Q1 2022 in order to show activity. But it seems the client Zen 4 will still be far away.

Zen 4 would likely follow Zen3 with that "hyperscalers first" strategy. Thus pushing the client Zen 4 (end maybe even server) back to Q4 or so. In the mean time, Intel will rush to launch refreshed Golden Cove products - Raptor Lake and Emerald Rapids. This assumes Intel will not magically release Meteor Lake & friends in 2022 as their recent PR suggested.

So Zen 4 has to be ready not for the OG Golden Coves but their refreshes or even newer gen.

 

[Joe NYC]

Two possibilities are stacked L2 and changing the L3 to be inclusive, although if one happens the other seems less likely by virtue of inclusive L3 making the most sense when L3 is relatively large vs L2.

Interesting idea. I wonder what the bottleneck for L2 is, if it can be expanded to stacked die without adding additional clocks. Also, if the process tweaks used for maximize the density of L3 would prevent stacked L2 running at required speed.

 

[Kedas]

Stacking dies, I'm wondering since TSV N5 on N5 is 3 quarters later than N7 on N7 that the TSV on N5 are even closer together than on N7.
In a way it makes sence that you want to keep the same number of TSV contacts like on N7 but it's on a smaller die.

 

[DrMrLordX]

Thus pushing the client Zen 4 (end maybe even server) back to Q4 or so.

Not if AMD repurposes failed Zen4 CCDs for Raphael.

So Zen 4 has to be ready not for the OG Golden Coves but their refreshes or even newer gen.

Pretty sure it will be. Raptor Lake looks oversold.

 

[Vattila]

Insightful look at the impact of cache vs core count on games:

Written article:

How CPU Cores & Cache Impact Gaming Performance

At some point you may have heard someone say that for gaming you need X amount of cores. Examples include "6 is more than enough cores," or...

www.techspot.com

Spoiler: summary

"When CPU limited in today's games, cache generally provides the largest performance gains and this is why we see less of a performance variation between the various Zen 3-based (Ryzen 5000 series) processors ranging from 6 to 16 cores. [...] AMD Zen 3 CPUs all feature 32MB of L3 cache per CCD, that's 32MB total cache in the case of the Ryzen 5 and Ryzen 7 parts, and Ryzen 9 getting a 64MB total broken into two separate dies. Intel CPUs though see a fundamental change in L3 cache capacity depending on core count. The 10th-gen 6-core i5 models get 12 MB of L3, 8-core i7’s get 16 MB, and the 10-core i9 20 MB."

PS. Interestingly, when AMD introduced the (much derided, and now most likely abandoned) marketing term "GameCache", they might have been preparing for the introduction of stacked L3 cache, now marketed as V-Cache.

 

[Ajay]

Geez, got way behind on this thread somehow. The signal to noise level is pretty low. This thread is trying to compete with on the level of a P&N thread. Guess I’ll just wait till some CPUs to be released rather than read all this endless bickering 🙄

 

[jamescox]

Geez, got way behind on this thread somehow. The signal to noise level is pretty low. This thread is trying to compete with on the level of a P&N thread. Guess I’ll just wait till some CPUs to be released rather than read all this endless bickering 🙄

I was involved in that discussion about 2 weeks ago or so. I kind of gave up on it. There are a bunch of technological arguments, but just because something is possible doesn’t mean that it will be a product. There doesn’t seem to be any room for the 4 high cache variant between top end Ryzen and Threadripper. They could make a large cache per core version of Threadripper without even using stacking. I have seen some gaming benchmarks with a Epyc 72F3 (8 cores, 32 MB per core, 256 MB total) vs. Intel Core i9-11900K; I don’t know how reliable they were though. The Epyc managed to win with a much lower clock, but not by a huge amount. The cpu can only do so much before you run into gpu bottlenecks. I am curious as to what Zen 3 Threadrippers will look like. AMD could make a version with very high cache per core, but the Epyc versions with huge cache per core are not cheap; the 72F3 is something like $2500, if you can get it. The supply of Milan processors seems to be very constrained right now.

At this point, I suspect the 1 vs. 4 consumer product is irrelevant since I think the 4 layer part will be a later product. They will likely intro the single layer part first and the 4+ layer part will be quite a bit later, probably closer to Zen 4 launch. There may be a lot of overlap between Milan-X3D and Genoa. Genoa is a completely new platform; new socket, new memory, new interconnect, etc. Parts of the server market move very slowly. They spec a machine and then stick with it for years. It will take quite a bit of time for Genoa to actually achieve market penetration. There are still some early adopters in HPC and a few other markets, but a lot of AMD’s sales are likely to be Milan or Milan-X3D for quite a while, even after Genoa. A Milan-X3D even with just a single layer of stacked cache will dominate everything else for some applications. That could be up to 768 MB of L3.