Info 64MB V-Cache on 5XXX Zen3 Average +15% in Games

[Kedas]

Well we know now how they will bridge the long wait to Zen4 on AM5 Q4 2022.
Production start for V-cache is end this year so too early for Zen4 so this is certainly coming to AM4.
+15% Lisa said is "like an entire architectural generation"

 

[Hitman928]

Regarding the building analogy, do we know how the data travel to this additional "floor"? Is it accessible at single place, like a floor would be via stairway/elevator shaft, or its connected on many points all over the surface of the chip?

There will be many TSVs for the routing between dies.

 

[Timmah!]

There will be many TSVs for the routing between dies.

Thanks!

 

[maddie]

Regarding the building analogy, do we know how the data travel to this additional "floor"? Is it accessible at single place, like a floor would be via stairway/elevator shaft, or its connected on many points all over the surface of the chip?

You missed this post : https://forums.anandtech.com/threads/speculation-zen-4-epyc-4-genoa-ryzen-6000.2571425/post-40514909

~24000 TSVs in Zen3 chiplet L3.

 

[Timmah!]

You missed this post : https://forums.anandtech.com/threads/speculation-zen-4-epyc-4-genoa-ryzen-6000.2571425/post-40514909

~24000 TSVs in Zen3 chiplet L3.

View attachment 45276

For sure i did miss it Thank you!

 

[jamescox]

You missed this post : https://forums.anandtech.com/threads/speculation-zen-4-epyc-4-genoa-ryzen-6000.2571425/post-40514909

~24000 TSVs in Zen3 chiplet L3.

View attachment 45276

This article indicates that the spacing between TSVs is 9 microns (9000 nm):

TSMC Teases 12-High 3D Stacked Silicon: SoIC Goes Extreme

www.anandtech.com

That is from last year though; these look like they may be closer, but it is hard to tell. The article talks about it going down to 0.9 microns, which is still 900 nm. It is a lot closer to being on die compared to micro-solder bump solutions (50 micron pitch), but it still is not the same as on die. It will be interesting to find out how this is logically arranged. The access latency is still very low even on 96 MB.

 

[cytg111]

Anyone else getting a Pentium-Pro vibe?

 

[DrMrLordX]

Anyone else getting a Pentium-Pro vibe?

Not entirely. I know what you're getting at - PPros had those on-chip 256k L2s in an era when, up to that point, L2 had been soldered onto the motherboard and ran at the bus speed rather than the CPU speed. Pentium Pro represented lots of other changes to the x86 world, however, that I don't see happening with v-cache-equipped Zen3. And honestly I don't expect the massive L3 of these v-cache CPUs to really outperform existing L3 in terms of bandwidth or latency. Socket 5 and Socket 7 L2 ran at 66 MHz in the days of Pentium Pro (100 mhz FSB Super 7 didn't come until later), whereas Pentium Pro L2 ran as high as 200 MHz, or higher if you were overclocking them (which some people did). L2 latency was hugely improved by PPro. I don't have numbers in front of me since that hardware is ancient by modern standards, but still. That on-board L2 of socket 5/socket 7 was slowwwww.

 

[Gideon]

And honestly I don't expect the massive L3 of these v-cache CPUs to really outperform existing L3 in terms of bandwidth or latency.

It's true that latency will, if anything, be slightly worse, but AMD promised 2 TB/s bandiwidth. That has to be a considerable improvement (source):

https://www.guru3d.com/articles-pages/amd-ryzen-9-5900x-and-5950x-review,21.html

 

[cytg111]

Not entirely. I know what you're getting at - PPros had those on-chip 256k L2s in an era when, up to that point, L2 had been soldered onto the motherboard and ran at the bus speed rather than the CPU speed. Pentium Pro represented lots of other changes to the x86 world, however, that I don't see happening with v-cache-equipped Zen3. And honestly I don't expect the massive L3 of these v-cache CPUs to really outperform existing L3 in terms of bandwidth or latency. Socket 5 and Socket 7 L2 ran at 66 MHz in the days of Pentium Pro (100 mhz FSB Super 7 didn't come until later), whereas Pentium Pro L2 ran as high as 200 MHz, or higher if you were overclocking them (which some people did). L2 latency was hugely improved by PPro. I don't have numbers in front of me since that hardware is ancient by modern standards, but still. That on-board L2 of socket 5/socket 7 was slowwwww.

Yea ok . I was mearly hovering around "same cpu core and different cache configs" .. and on top of that, IIRC, ppro had a beefed FPU on top of that as well.

 

[DrMrLordX]

It's true that latency will, if anything, be slightly worse, but AMD promised 2 TB/s bandiwidth. That has to be a considerable improvement (source):

Okay, fair point. Not sure how that additional bandwidth will affect things, but it should be interesting, especially if the branch prediction is good enough.

Yea ok . I was mearly hovering around "same cpu core and different cache configs" .. and on top of that, IIRC, ppro had a beefed FPU on top of that as well.

It did, it did. I was pretty revolutionary for its time. In some ways, the Klamath PIIs were a step backwards.

 

[Thibsie]

That on-board L2 of socket 5/socket 7 was slowwwww.

Until it became L3 thanks to K6-III.
What a beast this was at the time.

 

[Insert_Nickname]

Until it became L3 thanks to K6-III.
What a beast this was at the time.

Had an Epox MVP3-G5 with 2MB(!) L2 for work. Coupled with a K6-3 450MHz that thing was a complete beast.

It had a massive, for the time, 192MB RAM.

 

[DrMrLordX]

Until it became L3 thanks to K6-III.

Since we are going down history lane, you have to remember that the Super 7 boards were running 100 MHz fsb minimum, which was 50% faster than the original socket 5/socket 7 boards with on-board l2 cache running 66 MHz FSB. Latency and bandwidth both improved considerably. You'll also have to remember that older socket 7 boards had limitations on cacheable area (which were not well-documented at the time, but did exist). Those had been engineered out of Super 7 by the time of K6-III.

Just adding L3 to AMD's Super 7 lineup was a big deal in and of itself, but . . . can you imagine what v-cache would be like, if AMD halved the latency AND increased the size?

 

[lightmanek]

Had an Epox MVP3-G5 with 2MB(!) L2 for work. Coupled with a K6-3 450MHz that thing was a complete beast.

It had a massive, for the time, 192MB RAM.

Yep, I too had 2MB L2 or with my K6-III 400MHz, L3 cache on board.
Funny that your total RAM at the time will soon be equal to an L3 cache on consumer desktop CPU

Kind of first test I will run on that thing will be Quake 2 and Quake 3 timedemos

 

[IntelUser2000]

It's true that latency will, if anything, be slightly worse, but AMD promised 2 TB/s bandiwidth. That has to be a considerable improvement (source):

Bandwidth on current Zen 3's L3 cache is no worse when taking into account capacity.

The earlier versions of AIDA64 had problems measuring it properly. With proper testing Zen 3's L3 will measure 1TB/s.

 

[Thunder 57]

Funny that your total RAM at the time will soon be equal to an L3 cache on consumer desktop CPU

It's already happened. Depends on how far back you want to go I guess.

 

[Makaveli]

The earlier versions of AIDA64 had problems measuring it properly. With proper testing Zen 3's L3 will measure 1TB/s.

Also the bios he is using in the screenshot is 2311 which is

AMD AM4 AGESA V2 PI 1.1.0.0 PatchB

Has to be on 3302
- Update AMD AM4 AGESA V2 PI 1.2.0.1
- Fix the L3 cache performance in AIDA64

 

[Insert_Nickname]

Funny that your total RAM at the time will soon be equal to an L3 cache on consumer desktop CPU

Had the same feeling back when I got my Ryzen 3600. Back in 1999 32MB RAM was pretty common for mid-range systems. 20 years later, and that's the CPUs L3 cache. Now that's progress.

Got 32GB RAM to go along with it. The symmetry is beautiful, isn't it?

 

[zir_blazer]

With Cache L3 sizes snowballing I'm actually rather dissapointed about AMD having removed CAR (Cache-as-RAM) support, as told by Coreboot documentation about Zen Picasso. CAR was a rather minor and mostly unknow feature pretty much used exclusively by Firmware during Hardware initialization, which could setup the Cache in CAR mode so that there could be some usable memory that isn't the Processor GPRs (General Purpose Registers) themselves before the DRAM Controller and the system RAM behind it are fully operational. The Cache L3 isn't a lot, yet I always found interesing the idea of someone being able of getting MS-DOS working without having any memory modules installed. With snowballing Cache sizes, it should be possible to run a small video framebuffer for APUs, too. I always thought that it could be very useful to run a system like that if you could use the Firmware to run some diagnostics tools from a self contained Processor without requiring having memory installed, and pretty much consider it a fully operational computer for as long that you didn't go beyond the limited Cache memory boundaries.

 

[lobz]

So if it's 36 mm^2 X2 for two stacks of additional cache to get 12% more performance in gaming only, it seems very inefficient. The additional 72 mm^2 of silicon should be costly, and since Zen 3 is 81 mm^2, 88.8% more silicon should be giving 37% more performance by the square root rule of thumb.

And we should call that The Hougy Coefficient from now on.

 

[moinmoin]

With Cache L3 sizes snowballing I'm actually rather dissapointed about AMD having removed CAR (Cache-as-RAM) support, as told by Coreboot documentation about Zen Picasso. CAR was a rather minor and mostly unknow feature pretty much used exclusively by Firmware during Hardware initialization, which could setup the Cache in CAR mode so that there could be some usable memory that isn't the Processor GPRs (General Purpose Registers) themselves before the DRAM Controller and the system RAM behind it are fully operational. The Cache L3 isn't a lot, yet I always found interesing the idea of someone being able of getting MS-DOS working without having any memory modules installed. With snowballing Cache sizes, it should be possible to run a small video framebuffer for APUs, too. I always thought that it could be very useful to run a system like that if you could use the Firmware to run some diagnostics tools from a self contained Processor without requiring having memory installed, and pretty much consider it a fully operational computer for as long that you didn't go beyond the limited Cache memory boundaries.

Yeah, I remember when that news broke originally. Maybe AMD can make it work again, but my assumption is that AMD removed public support for this due to privately using CAR itself already for running AGESA/PSP and handling SCF with the extensive internal firmware that's likely running there.

 

[Doug S]

The Cache L3 isn't a lot

As someone whose first computer was a maxed out Atari 800 with a glorious 48K of RAM, I have to take issue with the claim that an L3 of tens of megabytes "isn't a lot"

 

[soresu]

As someone whose first computer was a maxed out Atari 800 with a glorious 48K of RAM, I have to take issue with the claim that an L3 of tens of megabytes "isn't a lot"

Even if Zen4 only increases EPYC4/TR5 core count to 96 we will actually see 1GB+ of SRAM cache in an x86 socket for the first time?

 

[Bigos]

Isn't it rumoured that a single Zen 3 chiplet can host up to 4 stacks of additional L3 cache, so 288MB in total? With that, you should get over 2GB of L3 cache with the highest-end Milan-X.

 

[igor_kavinski]

Talking about gigabytes of SRAM cache is getting a bit ahead of ourselves, methinks.