Olikan
Platinum Member
- Sep 23, 2011
- 2,023
- 275
- 126
This patent seems to fit exacly what AMD explained about Zen2 front end chages...
https://patents.justia.com/patent/10127044
https://patents.justia.com/patent/10127044
Firstly you have not understood how AMD CPUs are designed. AMD's CPU physical design is targetted at achieving high clock frequencies. So TSMC N7 is not a choice at all. AMD Zen CPUs had a max turbo boost of 4 Ghz. Zen+ CPUs performance had a max single core turbo of 4.35 Ghz. The mobile Ryzen 2700u had a max turbo of 3.8 Ghz. AMD is likely to target max clock frequencies atleast on par or higher than Zen+ for their 7nm Zen 2. So the only option is N7 HPC. AMD has already confirmed that all their 7nm CPUs and GPUs are using N7 HPC. This was confimed by Ashraf Eassa of The Motley Fool on twitter. But Ashraf has deactivated his twitter account a couple of months back.
btw I was one of the earliest people to propose that the Rome IO die could have L4 cache. But I think the chances of that are slim to none. Firstly for a significant amount of L4 cache (say 256 MB) AMD needs to go with 14HP and eDRAM for L4 cache. I think that process is not suitable for low cost high volume designs. Rome IO die needs to be low cost and low complexity. So its most likely based on the mature GF 14LPP node. Moreover if you look at the Zeppelin die and move all the IO and memory controller circuitry to a single die you would end up quite close to the 420 sq mm die size. AMD has probably spent some die area to maintain some cache information about the data stored on the L3 of each chiplet so that a chiplet can quickly look up that info to see if some data is in the L3 of another chiplet. But thats about it.
AMD's 8 core chiplet die is the basic building block for all of its 7nm products from server CPUs, desktop CPUs, desktop/notebook APUs , next gen console APUs (PS5/XB2). BTW AMD's move to chiplets is not only for servers. I expect almost every AMD design at 7nm to incorporate chiplets. AMD's move is very logical as its easier to yield smaller dies and you can match chiplets with similar characteristics to build SKUs across the product stack. The modularity and reusability of chiplets dictates that 8 cores is the right choice. Here is how I see the 7nm designs from AMD
Rome - 8 x 8=64C, 8MC, 128 PCI-E 4.0 lanes
Threadripper - 8 x 8=64C, 8MC, 128 PCI-E 4.0 lanes
Ryzen - 2 x 8=16C, 2MC, 32 PCI-E 4.0 lanes
Ryzen APU - 1 x 8 = 8C + Navi GPU chiplet 20 CU + 4 GB HBM2 cache, 2MC, 32 PCI-E 4.0 lanes
PS5/XB2 - 1 x 8= 8C + Navi GPU chiplet 80 CU, 256 or 384 bit GDDR6.
Here is how I see AMD's Navi product stack
Ryzen 7nm APU - 20CU, 1280 sp.
Navi 12 - 40CU , 2560 sp, 128 bit GDDR6 or 256 bit GDDR5X.
Navi 10 (PS5 GPU) - 80CU, 5120 sp, 256 bit GDDR6.
Navi 20 - 120CU, 7680 sp, 384 bit GDDR6.
I think Navi will be a good architecture and address long standing problems and drawbacks with GCN like scalability, perf and area efficiency, perf per CU, perf per sp. In fact I am optimistic because Sony is very aggressive with their PS5 graphics performance goals and Navi is heavily influenced by PS5's perf targets and design goals.
RR iGPU is called RAVEN.And we know that Navi 11 exist from a leaked roadmap, I assume Navi 11 is Mobile/desktop APU as Vega11 was.
RR iGPU is called RAVEN.
Vega11 is a canned midrange part.
https://www.amd.com/en/products/apu/amd-ryzen-5-2400gAMD said:AMD Ryzen™ 5 2400G with Radeon™ RX Vega 11 Graphics
Marketing names have no relation to their die naming schemes.
Marketing names have no relation to their die naming schemes.
VEGA10 is Vega56/64/WX8200/9100.
VEGA11 is ded.
RAVEN is RR iGPU bins.
VEGA12 is Vega16/20.
VEGA20 is Mi50/Mi60.
VEGA11 appeared on leaked ROCm roadmaps, together with everything else that made it out alive.Edited my post above.
VEGA11 appeared on leaked ROCm roadmaps, together with everything else that made it out alive.
https://videocardz.com/65521/amd-vega-10-and-vega-20-slides-revealedI couldn't find any such leaks outside of some super blurry rumor articles and it wasn't ever a part of AMD's ROCm presentations.
Marketing names have no relation to their die naming schemes.
VEGA10 is Vega56/64/WX8200/9100.
VEGA11 is ded.
RAVEN is RR iGPU bins.
VEGA12 is Vega16/20.
VEGA20 is Mi50/Mi60.
That's no refresh, it's a very different product.Vega 20 = 64CU (refresh)
Stop being stupid.Vega 11 = 11CU desktop/mobile apu
That's another HPC product aka Mi-Next.Navi20= maybe exists but I think it will be a refresh/rebrand of Navi10.
Leaked roadmaps are no rumors.So a blurry picture on a rumor article. . .
Leaked roadmaps are no rumors.
Yes, AMD told me this by releasing literally everything sans VEGA11.Who says it's a leaked roadmap and not a fake? Did AMD tell you this or the internet?
Most of the boards in the pic were either already released or officially announced by the time this "leak" happened, so that's not saying much. Also, not everything was released, unless you can show me where to buy a Vega 10x2 which was supposed to release last year.Yes, AMD told me this by releasing literally everything sans VEGA11.
Their shiny new Vega10-based dual GPU board is here.unless you can show me where to buy a Vega 10x2 which was supposed to release last year.
That's called an "internal roadmap" and you surely don't even remotely know how this silly industry works.This was a fake, and a bad one at that.
Their shiny new Vega10-based dual GPU board is here.
https://www.amd.com/en/press-releas...raphics-card-delivers-accelerated-performance
That's called an "internal roadmap" and you surely don't even remotely know how this silly industry works.
Proof-me-up, sempai.I work in this silly industry
Proof-me-up, sempai.
Ok. Here is where the confusion is so you can stop name calling.Yes, AMD told me this by releasing literally everything sans VEGA11.
btw I was one of the earliest people to propose that the Rome IO die could have L4 cache. But I think the chances of that are slim to none. Firstly for a significant amount of L4 cache (say 256 MB) AMD needs to go with 14HP and eDRAM for L4 cache. I think that process is not suitable for low cost high volume designs. Rome IO die needs to be low cost and low complexity. So its most likely based on the mature GF 14LPP node. Moreover if you look at the Zeppelin die and move all the IO and memory controller circuitry to a single die you would end up quite close to the 420 sq mm die size. .
8 cores + 16MB L3 take 44mm2 according to AMD s stated density improvement, if the L3 is extended to 32MB it would require 52mm2 on the chiplet (and tHis would led to 256MB total L3s), dunno what are the remaining 20mm2 used for as this seems a lot for IF.
I'd love to reduce my current systems down to one massively contained solution.