it also means 8C/16T CCXs.
If so, it will be interesting to see how the cores are wired up, i.e. what the interconnect topology looks like. Same goes for the topology for the chiplets. It is certainly no longer direct-connection for 8 cores, nor for 8 chiplets.
LOLOLOLOLOLOL.
https://twitter.com/chiakokhua/status/1041487772429705216
And https://twitter.com/peresuslog/status/1041514114789597185
Move on, nothing to see here.
And guys remember, Matisse IS 8C/16T design. That is one thing sure, at this moment.
LOLOLOLOLOLOL.
https://twitter.com/chiakokhua/status/1041487772429705216
And https://twitter.com/peresuslog/status/1041514114789597185
Move on, nothing to see here.
And guys remember, Matisse IS 8C/16T design. That is one thing sure, at this moment.
Aside that everything is BS anyway, I think some form of transparent real time memory/transport compression is overdue to alleviate any bandwidth congestion (most advantageous both in bandwidth limited high core MCMs like TR2 and in APUs).Memory compression? Isn't that normally a video card thing?
The diagram is not credible at all, none of this makes any sense.
And guys remember, Matisse IS 8C/16T design. That is one thing sure, at this moment.
Qualcomm uses... page 16-17Memory compression? Isn't that normally a video card thing?
With up to 8 cores it would probably make sense to use a ring-bus within the chiplet, as intel does. This would also allow unified L3 cache usage.I was thinking, the other day, that it would be wise for AMD to move away from 4-core CCXs to 8-core CCXs, assuming they could keep intracore latency the same. That way the consumer parts (Matisse) could be 1 CCX 8c/16t, avoid the inter-CCX latency penalty, and gain a big boost in a lot of apps currently not well-optimized for Zen/Zen+.
They could also just improve the latency between CCXes, keeping the high-level architecture the same as it's ridiculously horrible right now (2/3 of the latency between two dies and more than the memory latency)
If AMD will shy away from 4 core CCX it will mean that there will be no more NUMA and no more CCX design.For a minute there, it was like AMD was trying to make their own OpenPOWER CPU. Who knows, maybe they are . . .
chiplets!
I was thinking, the other day, that it would be wise for AMD to move away from 4-core CCXs to 8-core CCXs, assuming they could keep intracore latency the same. That way the consumer parts (Matisse) could be 1 CCX 8c/16t, avoid the inter-CCX latency penalty, and gain a big boost in a lot of apps currently not well-optimized for Zen/Zen+.