What scaling factor did you use for the cache? Note that SRAM shrinks down much more than logic when going 14LPP->7nm. According to wikichip, a high density SRAM bitcell is 0.027 µm² in TSMC 7nm and 0.064 µm² in Samsung/GloFo 14LPP, for a 0.42x shrink. The fact that SRAM scales so much better is basically why I think the caches got so big. It makes sense to spend more silicon on them when you get more in return.One issue is that, unless the Zen 2 cores are significantly taller and skinnier, there doesn't seem to be enough space on the die for two columns of 4 unless you kill the 32MB L3 cache rumour, or you stick a bunch of L3 on top of the columns in an asymmetric way. I was able to come up with this:
Which just barely squeezes everything including 32MB of L3 inside the die, and that's with transistor scaling a bit on on the liberal side.