Zen APUs made by GloFo, 14nm FinFET node, and packaged by Amkor

[ShintaiDK]

Why dont you prove the difference you claim exist instead of making up more stuff?

I can give you a hint that your claim that IB uses more power than SB in AVX is 100% BS. Not that anyone should be surprised of this.

 

[AtenRa]

Why dont you prove the difference you claim exist instead of making up more stuff?

I have already posted a nice link, go to page 34 and read.

 

[ShintaiDK]

I have already posted a nice link, go to page 34 and read.

Yes, and like the node/library it seems you have no idea what you post. But just make stuff up as you go.

Also it shows nothing of your claim:

Dont compare SB AVX vs IV AVX. The two CPU designs are not the same, Ivy uses more power and it is faster than the SB in AVX load.

 

[ElFenix]

You are forgetting we are porting the same CPU design to 14nm LPP. If Kaveri can operate at 4GHz at 95W TDP on the 28nm Planar, it can certainly be clocked at 5GHz at lower TDP if manufactured at 14nm LPP.

Example,

At 14nm LPP you can have a 4GHz Kaveri at 35-45W TDP

OR

A 5GHz Kaveri at 65W TDP

OR

A 5.5GHz Kaveri at 95W TDP

isn't there a thread on this topic already? why are you putting this in a zen thread?

edit: do you want me to move the last ~40 posts to a new thread?

 

[coercitiv]

At 14nm ??? easily.

Sandy Bridge 4c/8t @ 3.6Ghz and 25W TDP. Easily. Ok.

So we could have had 15W TDP 4c/8t Sandy Bridge @ 2.6Ghz, but Intel chose to give us 2c/4t Skylake @ 2.6Ghz, trading half the number of cores for 20-25% increased IPC. Madness!

This is an extraordinary finding! If AMD hits Sandy Bridge performance & efficiency levels with Zen they will obliterate the competition!

 

[AtenRa]

isn't there a thread on this topic already? why are you putting this in a zen thread?

edit: do you want me to move the last ~40 posts to a new thread?

What thread are you referring to ?? this thread here is not only about ZEN but 14nm also according to the thread title.

 

[AtenRa]

Sandy Bridge 4c/8t @ 3.6Ghz and 25W TDP. Easily. Ok.

So we could have had 15W TDP 4c/8t Sandy Bridge @ 2.6Ghz, but Intel chose to give us 2c/4t Skylake @ 2.6Ghz, trading half the number of cores for 20-25% increased IPC. Madness!

This is an extraordinary finding! If AMD hits Sandy Bridge performance & efficiency levels with Zen they will obliterate the competition!

Intel Core i7 6700T
14nm

4C 8T
2.8GHz base on a vastly improved IPC architecture vs SB
4-5x the iGPU performance over SB

AT ONLY 35W TDP

It would be really easy to have a 25-30W TDP SB Core i7 2700K at 14nm.

 

[ElFenix]

What thread are you referring to ?? this thread here is not only about ZEN but 14nm also according to the thread title.

only insofar as 14nm intersects with zen.


so, why are you derailing this thread?

 

[deasd]

AM4 Socket will be µOPGA and it will have 1331 pins
http://www.bitsandchips.it/english/5...have-1331-pins

If true, those additional pin must mean something, such as HBMs......

 

[AtenRa]

only insofar as 14nm intersects with zen.


so, why are you derailing this thread?

I dont believe im derailing this thread by talking about GloFos 14nm process and its possibilities but if you feel i do ill stop.

We had a nice conversation on the matter but no worries.

 

[coercitiv]

Intel Core i7 6700T 14nm 4C 8T
2.8GHz base on a vastly improved IPC architecture vs SB
4-5x the iGPU performance over SB

AT ONLY 35W TDP

It would be really easy to have a 25-30W TDP SB Core i7 2700K at 14nm.

35W is 40% more power than 25W.
3.6Ghz is 30% higher than 2.8Ghz, which translates in over 50% more power

This is the perfect example to show how far off your estimate is, with the only argument in your favor being increased power usage from the improved architecture. Again, 20-25% improved IPC cannot account for more than 2x 100% increase in power usage, that alone would kill the new arch.

 

[Dresdenboy]

AM4 Socket will be µOPGA and it will have 1331 pins
http://www.bitsandchips.it/english/5...have-1331-pins

If true, those additional pin must mean something, such as HBMs......

Or an IVR.

 

[krumme]

Or an IVR.

Why is that ??

 

[cytg111]

404

 

[ElFenix]

Or to their private messages ?

It's done. Let it be.

 

[Dresdenboy]

Why is that ??

A chance for improved power efficiency of the whole chip.

 

[krumme]

A chance for improved power efficiency of the whole chip.

Yea i get that, but how many pins do you need for that?

 

[MrTeal]

Or an IVR.

Wouldn't an IVR (and HBM for that matter) reduce the number of pins needed?

~350 extra pins doesn't really seem necessary from what we've seen advertised so far. That's just about the right number for another dual channel MC if they want to make the socket extensible in the future, but that seems unlikely.

 

[krumme]

Havnt Carrizo per IP adaptive voltage?

 

[cytg111]

-> dresdenboy -> krumme

off topic question of the day ; does the PIT(Programmable Interval Timer) still factor into todays x86 designs/concepts or is it called something else? How and where?

- or just ignore at will 😉

 

[krumme]

Hsa?

 

[IntelUser2000]

Yea i get that, but how many pins do you need for that?

The pin count increase tells nothing. Intel increased pin count without making any big changes.

Though we can guess. Maybe a high power part like 220W will be more common. Perhaps a 150W APU + 70W CPU for a true mid range replacement?

 

[krumme]

Hmm. Who wants 220w parts today?
If its something big it can be the "private messages". I dont know crap about it but on a interposer how fast transmissions is possible - can you eg share L3/L4 cache?

 

[Phynaz]

Removed

 

[cytg111]

404