Discussion Zen 7 speculation thread

[AMDK11]

It's still not as beefy as other designs, I agree with the general sentiment there. But the large gap that AMD used to have vs Intel in achieving similar IPC with much smaller core structures seem to have shrunk.
TBF, I think AMD missed what they wanted to hit with Zen 5. The area and perf/ipc topic has been well discussed by this point, but I wonder if there is anyone testing Zen 3 vs Zen 2 core power curves.

Zen lived up to expectations. Agner Fog demonstrated that Zen5 executes 6 instructions per clock cycle (rarely 8). The main goal of Zen5 was to expand, deepen, and redesign it. This is the foundation for future generations.

I don't know what you expected. 40-50% was never true, nor was it even planned. You're looking at this through the lens of Zen1, which achieved such a large IPC increase only because the ST Bulldozer-Excavator processors had poor performance.

For Zen5 to achieve an IPC increase greater than an average of +13% for INT and +24% for FP, AMD would have had to further expand the core structures, which would have increased design and testing time.

LionCove supposedly has larger structures, but this doesn't translate into an IPC advantage over Zen5. I won't mention the L3 cache, especially since Zen5's advantage in this regard is enormous.

 

[adroc_thurston]

which would have increased design and testing time

Area and power are the limits, not design cycle times.

 

[AMDK11]

Area and power are the limits, not design cycle times.

This is the main reason.

 

[adroc_thurston]

This is the main reason.

?

 

[AMDK11]

?

Area and power are the main drivers for expanding Zen cores. But it's also about project time, so as not to overdo it.

 

[adroc_thurston]

But it's also about project time, so as not to overdo it.

Bloating the core takes no time.
ARM does it yearly.

 

[AMDK11]

Bloating the core takes no time.
ARM does it yearly.

Yes? And what about the recent increase in IPC?

You mean the move from M3 to M4 and the average IPC increase for INT +8% and FP +9%? There's definitely been a huge increase in core structures

 

[Mopetar]

Apple launched M4 ~6 months after they launched M3. An 8% IPC uplift in that short time span is actually impressive.

 

[Geddagod]

Zen lived up to expectations. Agner Fog demonstrated that Zen5 executes 6 instructions per clock cycle (rarely 8). The main goal of Zen5 was to expand, deepen, and redesign it. This is the foundation for future generations

The main purpose of LNC was to expand, deepen, and redesign it. Same for SNC too. All these cores were foundations for future generations /s.
This is not a good excuse.

I don't know what you expected. 40-50% was never true, nor was it even planned. You're looking at this through the lens of Zen1, which achieved such a large IPC increase only because the ST Bulldozer-Excavator processors had poor performance.

In my previous comments in this thread I explicitly compared this to Zen 3.

For Zen5 to achieve an IPC increase greater than an average of +13% for INT and +24% for FP, AMD would have had to further expand the core structures, which would have increased design and testing time.

The problem with this thinking is exactly what led the P-core team astray. You can not spam "expand ROB capacity" or just blow up the core structure capacities every time you want to increase IPC.

LionCove supposedly has larger structures, but this doesn't translate into an IPC advantage over Zen5.

Exactly, so clearly neither does Zen 5 to achieve a better IPC uplift than what it already has.

 

[Doug S]

Apple launched M4 ~6 months after they launched M3. An 8% IPC uplift in that short time span is actually impressive.

Launching M4 6 months after M3 doesn't tell us anything about the lag between the design completion of the CPU cores in M3 vs those in M4. The M3 has the same P core as A17P, which was launched in September 8 months before the M4 iPad Pro. Apple needs to start production of iPhone SoCs further ahead of launch than the M4 in the iPad Pro, because they are shipping 10+ million iPhones launch day. That gets the gap to at least 9 months.

There's another factor as well. The iPhone ships on a really hard schedule, Srouji doesn't ever want to go to Tim Cook and say "sorry we need another revision on the iPhone SoC to fix a critical bug we found so the product isn't going to make the September launch window". They'll have some slop built into its development schedule to insure there's room for that sort of thing, which adds a few more months to "core design complete" gap between A17P/M3 and M4, bringing the gap to a year. No product using Apple Silicon has a hard schedule like the iPhone, so they don't need to worry about an "oops". They'll just release later. Who knows, maybe something like that is the reason for the rumors about M5 Macs slipping into next year.

So I see that IPC uplift as being a normal year to year gain, not something achieved in 6 months. AMD is more like Apple Silicon in its release schedule - it is released when it is done, there are no products with set schedules depending on it (at least not as far as AMD is concerned, AMD's OEMs may feel differently)

 

[AMDK11]

Apple launched M4 ~6 months after they launched M3. An 8% IPC uplift in that short time span is actually impressive.

So you're suggesting that design + testing + silicon implementation + validation will only take 6 months?

The project was carried out in parallel and lasted significantly longer than 6 months.

 

[Geddagod]

Yes? And what about the recent increase in IPC?

You mean the move from M3 to M4 and the average IPC increase for INT +8% and FP +9%? There's definitely been a huge increase in core structures

A +19 INT and +25% FP uplift in spec2017 (Geekerwan) for a 18% increase in core area is really, really good. I imagine a good chunk of the area increase there was actually from the switch to HD to HP cells for the P-core. Meanwhile Zen 5 is a nearly 40% area increase without the L2 block + CPL/clock blocks compared to Zen 4, for a perf uplift that was less than what the M4 got.
Arch wise...

Capacity increases vs Last Gen:	Zen 5	M4
ROB capacity	+40%	+37%
Rename Width	+33%	+11%
Store Buffer capacity	+63%	+11%
Load Buffer capacity	+130%	-9%
Total scheduler entries	+63%	+16%
INT reg file	+7%	+21%
FP reg file	+100%	-11%

For power, I don't think anyone knows how the M4 P-core vs the M3 P-core fares at low power, because you can't limit frequency/power per core on Apple silicon like you can on Intel or AMD or android stuff afaik, but Zen 5 doesn't shine there either...

 

[AMDK11]

The main purpose of LNC was to expand, deepen, and redesign it. Same for SNC too. All these cores were foundations for future generations /s.
This is not a good excuse.

In my previous comments in this thread I explicitly compared this to Zen 3.

The problem with this thinking is exactly what led the P-core team astray. You can not spam "expand ROB capacity" or just blow up the core structure capacities every time you want to increase IPC.

Exactly, so clearly neither does Zen 5 to achieve a better IPC uplift than what it already has.

First, ARM has instructions with a fixed length of 4 bytes.

x86 has variable-length instructions from 1 to 15 bytes, translated by the x86 decoder to a fixed-length 64-bit instruction.

From what I understand, Apple's cores, although wide, are relatively simpler and incompatible with previous generations, which is why they place a significant emphasis on software programming.

Apple places a significant emphasis not on the cores themselves, but on software written specifically for Apple cores.

For x86, engineers must demonstrate greater software brilliance. Zen5 has the most powerful predictor ever developed within the given process area budget and transistor density.

Presenting ARM here in the context of the x86 microarchitecture misses the point. Because x86 means backward compatibility, high IPC, and clock speed. I wouldn't trade it for any other platform just because its simpler microarchitecture allows for higher IPC thanks to its heavy emphasis on software.

95-99% of people have no idea about IPC, let alone the core microarchitecture, so it's not one of the main factors considered when choosing.

 

[Doug S]

From what I understand, Apple's cores, although wide, are relatively simpler and incompatible with previous generations, which is why they place a significant emphasis on software programming.

What the heck are you talking about here? You think if you get an M4 Mac to replace an M3 Mac you have to recompile all your code to run on it??

 

[AMDK11]

What the heck are you talking about here? You think if you get an M4 Mac to replace an M3 Mac you have to recompile all your code to run on it??

Didn't ARM64 require recompiling the software from ARM32?

Secondly, does ARM have as powerful FP and INT SIMD 512 as Zen5?

 

[adroc_thurston]

Didn't ARM64 require recompiling the software from ARM32?

Yeah, only that in Apple lands it happened in 2013.
macOS deprecated 32b software eons ago. That's why the transition went relatively smoothly.

 

[AMDK11]

ARM is not a competitor to x86. Apple's ARM market share in PCs and HPC is marginal, and x86 has a huge software base and backward compatibility. No one, especially those who don't know anything about it (95% of people), will switch to Apple's Mx just because of its higher IPC. This is especially true since the x86 software base is vast. Much of this software is open source.

Apple isn't competitive with me in any way, especially when it comes to the PC platform. I also want an x86-compatible laptop. Apple is a niche market.

ARM (Apple, among other things, has nothing to do with x86 PCs). This thread is about Zen7, and let's focus on the advanced x86 platform instead of immediately reducing the discussion to Apple or other ARM solutions. Perhaps we should also start discussing it in the context of IBM. In my opinion, it's pointless.

Those who consider Apple Mx their idol and role model should discuss it in a different thread.

This thread is about x86 Zen7. So let's focus on that topic instead of the completely different programming model that is ARM.

 

[Geddagod]

First, ARM has instructions with a fixed length of 4 bytes.

x86 has variable-length instructions from 1 to 15 bytes, translated by the x86 decoder to a fixed-length 64-bit instruction.

From what I understand, Apple's cores, although wide, are relatively simpler and incompatible with previous generations, which is why they place a significant emphasis on software programming.

Apple places a significant emphasis not on the cores themselves, but on software written specifically for Apple cores.

For x86, engineers must demonstrate greater software brilliance. Zen5 has the most powerful predictor ever developed within the given process area budget and transistor density.

What's nice about spec2017 is that it largely eliminates such software considerations. In fact, doing stuff like that invalidates spec2017 submissions. IIRC there was a whole thing about SPR? EMR? doing something like that and having the submissions cancelled.

As for your statement about the Zen 5 BPU... maybe. We don't have any Apple silicon BP accuracy results afaik. But AMD's BPU kinda has to be more accurate than ARM stuff, since their pipelines are also longer, making a branch mis predict worse.

A bit of a tangent, but also why I believe LNC's BPU is no real improvement (or even worse) than RWC's - I don't think Intel spent much time here since they reduced the branch mis predict penalty anyway. Not that this makes the situation vs AMD any better, since afaik their pipeline is still longer if not similar in length.
But there's also both power and area considerations in play here for the BPU. I wouldn't stretch that to say the "given area budget"

 

[Geddagod]

ARM is not a competitor to x86. Apple's ARM market share in PCs and HPC is marginal, and x86 has a huge software base and backward compatibility. No one, especially those who don't know anything about it (95% of people), will switch to Apple's Mx just because of its higher IPC. This is especially true since the x86 software base is vast. Much of this software is open source.

Apple isn't competitive with me in any way, especially when it comes to the PC platform. I also want an x86-compatible laptop. Apple is a niche market.

I swear, people get so defensive about x86 whenever architectural comparisons between cores on the two different ISAs are drawn up.

 

[MS_AT]

A +19 INT and +25% FP uplift in spec2017 (Geekerwan) for a 18% increase in core area is really, really good. I imagine a good chunk of the area increase there was actually from the switch to HD to HP cells for the P-core. Meanwhile Zen 5 is a nearly 40% area increase without the L2 block + CPL/clock blocks compared to Zen 4, for a perf uplift that was less than what the M4 got.
Arch wise...

You should have included the absolute values in the table too to present full picture. As iirc most of these structures are bigger on M4 than on Zen5.

 

[AMDK11]

I swear, people get so defensive about x86 whenever architectural comparisons between cores on the two different ISAs are drawn up.

Exactly. I'll reiterate that 95-99% of people have no idea about IPC, let alone micro-architectures.

For me, Apple's MX is just a curiosity about what else can be done to improve IPC through software, etc. It's not a real competitor to x86, and I'd never consider replacing x86 with an ARM processor. But everyone has a choice and chooses what suits them.

 

[Geddagod]

You should have included the absolute values in the table too to present full picture. As iirc most of these structures are bigger on M4 than on Zen5.

For a M4 vs Zen 5 comparison, sure.
But I'm specifically referencing to the tock itself, or the improvement between generations.

 

[Geddagod]

Exactly. I'll reiterate that 95-99% of people have no idea about IPC, let alone micro-architectures.

For me, Apple's MX is just a curiosity about what else can be done to improve IPC through software, etc. It's not a real competitor to x86, and I'd never consider replacing x86 with an ARM processor. But everyone has a choice and chooses what suits them.

I prob would never get a mac too. Too addicted to valorant and hoi 4 lol

 

[AMDK11]

You should have included the absolute values in the table too to present full picture. As iirc most of these structures are bigger on M4 than on Zen5.

Yes, most structures (buffers) are larger, but Zen5 has more advanced control logic. Buffers alone aren't everything. The x86 design alone makes the control logic incredibly versatile and advanced, as it takes the lead in improving software processing compared to ARM logic, which strictly controls the writing of highly optimized software.

 

[poke01]

Exactly. I'll reiterate that 95-99% of people have no idea about IPC, let alone micro-architectures.

For me, Apple's MX is just a curiosity about what else can be done to improve IPC through software, etc. It's not a real competitor to x86, and I'd never consider replacing x86 with an ARM processor. But everyone has a choice and chooses what suits them.

No one is telling you should switch. It’s general academic discussions about different ISAs. Also Zen7 is so far out you would get tangents like this.