Discussion Zen 7 speculation thread

[511]

What do you mean proper support? do you want subtests like AES-XTS to come back?

Also not every work flow benefits from AVX512, AV1 encoding for example doesn’t benefit that much. It’s around a 10-20% improvement at best.

AES is un ironically a good subtest cause it's actually used in your daily life ... More than Object Detection and Background Blur on a Laptop

 

[511]

So it’s okay if Geekbench boosts an x86 processor in GB5 by 2x and doesn’t boost ARM scores.

They didn’t subtract anything for x86, in fact it’s even greater thanks to AVX512-VNNI

Without AVX512-VNNI and AVX-VNNI support total scores for Zen5 and Lion Cove would be lower by 10% as well in GB6.

It's still part of the core unlike SME which is shared between cores we are testing a single core not single core + accelerators.
I am not in favour of cluster accelerators creeping in ST.

 

[Joe NYC]

Are you being ignorant on purpose?

Object detection in Geekbench 6 favoured AVX512-VNNI by a factor of 2.5x way before SME even came into the picture.

It is about removal of AES-XTS subtest from GB 6 that knocked off 10% of Zen 5 score (before GB 6 started adding Apple / Arm optimizations)

Why? Here is why. GeekBench 5 scores:
9950x AVX-Off: 2425
M4: 2628
9950x AVX-On: 2652

That's why everybody's mind was wiped about GeekBench 5.

If there is a perception of GeekBench being a shill for Apple and Arm, and then they do everything to confirm it with their actions, why not believe them, and take them for shills?

 

[poke01]

It's still part of the core unlike SME which is shared between cores we are testing a single core not single core + accelerators.
I am not in favour of cluster accelerators creeping in ST.

i agree but it’s likely to be common place over the coming years. What if there are multiple math mul accelerators within a CPU core, does that make it okay?

That would go against your argument I think

AES is un ironically a good subtest cause it's actually used in your daily life ... More than Object Detection and Background Blur on a Laptop

Umm you ever did a teams meeting or seen recent video editing apps that use ML? more apps make use of AVX-VNNI and is more a real use case for more users than crypto especially with OpenVINO.

 

[511]

Umm you ever did a teams meeting or seen recent video editing apps that use ML? more apps make use of AVX-VNNI and is more a real use case for more users than crypto especially with OpenVINO.

Crypto is used by to send and receive all that encrypted data and send telemetry to MSFT wherever there is Sharing of data online there is crypto.

 

[511]

Big problem with AVX-2/AVX-512 there are still some _mm256 intrinsic that requires AVX-512 like _mm256_xor_epi32(I think that was the name ) which should have been able to use with AVX-2 but also broadcasting stuff.

 

[511]

Big problem with AVX-2/AVX-512 there are still some _mm256 intrinsic that requires AVX-512 like _mm256_xor_epi32(I think that was the name ) which should have been able to use with AVX-2 but also broadcasting stuff.

 

[poke01]

Crypto is used by to send and receive all that encrypted data and send telemetry to MSFT wherever there is Sharing of data online there is crypto.

AES-XTS is for local storage encryption like Bitlocker.

Subtests that use ML are much more useful and AMD is adding even more extensions in Zen6/7 because that’s where the industry is heading.

Intel Optimization at Netflix

Netflix Performance Engineering work closely with Intel in optimizing workloads hosted on AWS public cloud. We have successfully integrated…

medium.com

 

[511]

AES-XTS is for local storage encryption like Bitlocker.

Website uses AES just not AES-XTX what about SHA-256?

 

[Doug S]

It's still part of the core unlike SME which is shared between cores we are testing a single core not single core + accelerators.
I am not in favour of cluster accelerators creeping in ST.

So should ST tests be required to do something to prevent using more than one core's "share" of a shared L2/L3 cache? If you don't want to let one core use a whole cluster's worth of SME why are you OK with one core using the entire chip's massive L3 in something like a 9950X3D?

Rules for thee but not for me, I guess.

 

[511]

So should ST tests be required to do something to prevent using more than one core's "share" of a shared L2/L3 cache? If you don't want to let one core use a whole cluster's worth of SME why are you OK with one core using the entire chip's massive L3 in something like a 9950X3D?

Rules for thee but not for me, I guess.

Memory Hierarchy is part of the Core but not accelerators if you have to cheat benches do it properly use NPU not make up a specific cluster just to cheat I prefer proper SPEC anyway not meme bench if I go by this jt should be criminal for a core to use all the Ram Bandwidth...

 

[poke01]

Memory Hierarchy is part of the Core but not accelerators if you have to cheat benches do it properly use NPU not make up a specific cluster just to cheat I prefer proper SPEC anyway not meme bench if I go by this jt should be criminal for a core to use all the Ram Bandwidth...

SME is standardised though in the ARM ecosystem, whereas NPUs APIs and features differ from each vendor and barely any support from apps for the NPU on Windows and Android.

That’s what makes CPU ML extensions great, they are all standardised. Just avoid Geekbench 6 if it annoys you, like you said SPEC when done properly shows the true performance of a core in INT and FP

 

[Nothingness]

Memory Hierarchy is part of the Core but not accelerators if you have to cheat benches do it properly use NPU not make up a specific cluster just to cheat I prefer proper SPEC anyway not meme bench if I go by this jt should be criminal for a core to use all the Ram Bandwidth...

What makes you think accelerators don't use the memory hierarchy? SME certainly does; you can see L2 effect here: https://scalable.uni-jena.de/opt/sme/micro.html

 

[511]

What makes you think accelerators don't use the memory hierarchy? SME certainly does; you can see L2 effect here: https://scalable.uni-jena.de/opt/sme/micro.html

I never implied that I only meant that cheating in GB with cluster level hacks is something I dislike.
I won't have problem if it's part of the core.

 

[Nothingness]

I never implied that I only meant that cheating in GB with cluster level hacks is something I dislike.
I won't have problem if it's part of the core.

Sorry, I misunderstood what you wrote

There's still a difference between a "standard" accelerator and an SME block in a cluster: sharing of some registers, instruction decoding partly done by the CPU. The coupling is much tightier than with a HW accelerator.

That said I understand your point. I think a fairer way would be to compare things when run in MT: in that case the (useful) impact of SME would be decreased compared to ST.

 

[Doug S]

Memory Hierarchy is part of the Core but not accelerators if you have to cheat benches do it properly use NPU not make up a specific cluster just to cheat I prefer proper SPEC anyway not meme bench if I go by this jt should be criminal for a core to use all the Ram Bandwidth...

Who says "memory hierarchy is part of the core"? What about systems with unified memory between the CPU and GPU, if everything that's under the memory hierarchy is "part of the core" by your definition, then such systems should be able to use GPU to speed up benchmarks right?

The SME instructions are part of the instruction stream, and are executed the same way as any other instructions. The location of the execution unit being accessible by any core in the cluster, rather than being located in the core shouldn't matter. That execution unit shares the L2 with the other cores in the cluster, and shares the SLC with the rest of the cluster, other clusters, the GPU, the NPU (you get it, with essentially EVERYTHING else in the SoC)

People who want x86 to "win" are butt hurt that ARM is getting some benefit from non traditional instructions for once, instead of such benefits being reserved for stuff like AVX-512. If Zen 7 included an SME like matmul unit that was shared between cores but was twice the size of Apple's and therefore boosted benchmarks by twice as much 100% you'd change your tune on this lol

What about systems that have a single "prime" core that runs faster than the rest, or is of a different uarch than the rest? Is that cheating, since that one core's performance can't be replicated across other cores? What about systems that will turbo one or a small number of cores if that's the only thing happening, but in real world situations where there are other tasks those cores don't often run at that higher speed? Think it is unfair to measure ST with just one core active thus allowing that core to run a mostly unrealistically high speed?

Face it, benchmarking is a lot more complicated than it used to be, and promises to become even more complicated in the future. There are always things you can see as "unfair" if you feel it disadvantages the CPU you're rooting for. Your arguments remind me of football fans who claim their favorite team is always the victim of bad calls from the refs. They always get called for holding or PI while the other teams hold or commit PI on every play and it is hardly ever called. When you look at things with a rooting interest you are never going to be happy with what you get.

I'd suggest if the way Geekbench operates bothers you so much maybe you should ignore its results and use SPEC, but you probably think SPEC is biased against x86 too...

 

[511]

'd suggest if the way Geekbench operates bothers you so much maybe you should ignore its results and use SPEC, but you probably think SPEC is biased against x86 too...

I don't think that maybe it's your opinion 🙂 but not mine

Face it, benchmarking is a lot more complicated than it used to be, and promises to become even more complicated in the future. There are always things you can see as "unfair" if you feel it disadvantages the CPU you're rooting for. Your arguments remind me of football fans who claim their favorite team is always the victim of bad calls from the refs. They always get called for holding or PI while the other teams hold or commit PI on every play and it is hardly ever called. When you look at things with a rooting interest you are never going to be happy with what you get.

Well for one it is unfair benchmark how can I have a extra dedicated silicon that is used in both ST/MT and gives the same performance nearly in both

 

[StefanR5R]

There are a few people here who talk about Geekbench as if it was a cross-platform benchmark.
It is not a cross-platform benchmark.
(It can be had for a couple of platforms, but it cannot be used to compare different platforms.)

How to make a cross-platform benchmark:
– Make the source code available to those who want to run the benchmark.
– Provide guidelines about how to compile, to run, and to publish results to those who want to publish benchmark results.
– (Make these guidelines into mandatory rules to those who have commercial interest behind publishing benchmark results.)

So again: Why are folks here spending so many posts on Geekbench, especially in the context of performances of different platforms?

Edit:
The above is for "synthetic" benchmarks. Not for benchmarks of cross-platform closed-source applications. Such benchmarks should be coded and compiled as close to their parent application as possible. The results of such a benchmark show how good or bad the application runs on the platforms, not how good or bad the platforms are.

because a lot of these extensions in SPR will be added to Zen7 which Geekbench already supports,

So when Zen 7 is out, perhaps the Geekbench authors work to optimize Geekbench to be accelerated by Zen 7. Or Geekbench is accelerated by Zen 7 by accident. Or neither of this. In *any of these cases*, what's so life-changing about how fast Geekbench can be run on Zen 7? (Life-changing for those who mistake Geekbench for a cross-platform benchmark perhaps.)

 

[OneEng2]

There are a few people here who talk about Geekbench as if it was a cross-platform benchmark.
It is not a cross-platform benchmark.
(It can be had for a couple of platforms, but it cannot be used to compare different platforms.)

How to make a cross-platform benchmark:
– Make the source code available to those who want to run the benchmark.
– Provide guidelines about how to compile, to run, and to publish results to those who want to publish benchmark results.
– (Make these guidelines into mandatory rules to those who have commercial interest behind publishing benchmark results.)

So again: Why are folks here spending so many posts on Geekbench, especially in the context of performances of different platforms?

Because it is easy to do

 

[Geddagod]

There are a few people here who talk about Geekbench as if it was a cross-platform benchmark.
It is not a cross-platform benchmark.
(It can be had for a couple of platforms, but it cannot be used to compare different platforms.)

How to make a cross-platform benchmark:
– Make the source code available to those who want to run the benchmark.
– Provide guidelines about how to compile, to run, and to publish results to those who want to publish benchmark results.
– (Make these guidelines into mandatory rules to those who have commercial interest behind publishing benchmark results.)

So again: Why are folks here spending so many posts on Geekbench, especially in the context of performances of different platforms?

It absolutely can and should.
Here's Intel doing exactly this:

Here's AMD doing exactly this:

And obv Qcomm does it too.
Everyone compares across platforms.

 

[StefanR5R]

Vendors' marketing staff putting null-info comparisons into their marketing slides doesn't necessitate that we pull the discussion here down to that level.

 

[Geddagod]

Vendors' marketing staff putting null-info comparisons into their marketing slides doesn't necessitate that we pull the discussion here down to that level.

Vendors choose marketing to put themselves in the most advantageous situation. Even a best case scenario is that they use benchmarks to reflect the actual performance of their product. If they feel like they are disadvantaged in the comparison, or it's not accurate, why would they use the benchmark?
These companies have no problem about whining about "real world performance" vs benchmarks in the past. These companies have no problems with messing with spec2017 compilers and such to get better scores vs the competition for their graphics and marketing.

 

[OneEng2]

Vendors choose marketing to put themselves in the most advantageous situation. Even a best case scenario is that they use benchmarks to reflect the actual performance of their product. If they feel like they are disadvantaged in the comparison, or it's not accurate, why would they use the benchmark?
These companies have no problem about whining about "real world performance" vs benchmarks in the past. These companies have no problems with messing with spec2017 compilers and such to get better scores vs the competition for their graphics and marketing.

The nature of the beast .

If you are ahead in anything, be sure to point it out. If you lag in something, don't talk about it.

 

[soresu]

Here's Intel doing exactly this:

Oh how sneaky of them to only compare 1T figures.

 

[mikegg]

NO, as the added Mod comment says, no trolling or baiting. We have heard enough about Intel.

Second, small cores without SMT and avx-512 are very lacking. Just SMT alone doubled (or greatly increases) the number or cores. Once you add ability for other things like avx-512 they are lost in the dust.

How was my post trolling or baiting? Can you specify exactly which sentence was doing that? Meanwhile, you have actual trolls and baiters that have 1 or 2 year old accounts doing it but no warning to them.

There is a difference between me saying things that aren't the popular opinion on this thread and baiting/trolling.