Discussion Zen 7 speculation thread

[DrMrLordX]

Market didn't understand it just like optane and it got killed

Acshually, it's arguable that 10nm killed Phi.

 

[511]

10nm killed Intel tbh alongside LG

 

[regen1]

Acshually, it's arguable that 10nm killed Phi.

Borked/delayed 10nm launch might have contributed to the death of the Xeon Phi line but hard to know if leadership then was keen to continue the line even without 10nm disaster.
Original Aurora SC(Argonne) contract was for Knights Hill.
Just shows how badly Ponte Vecchio faired overall(its biggest contract was pre-earned by another product, perf targets changed with delays but still). Made sense to cancel Rialto Bridge, would have been another complex design with little impact.

 

[regen1]

Apparently, of all the Classic and Dense versions from Zen 4 till Zen 7,
Zen 7 will have the biggest IPC gap between its Classic and Dense version.

 

[511]

Apparently, of all the Classic and Dense versions from Zen 4 till Zen 7,
Zen 7 will have the biggest IPC gap between its Classic and Dense version.

Why ?

 

[adroc_thurston]

Apparently, of all the Classic and Dense versions from Zen 4 till Zen 7,
Zen 7 will have the biggest IPC gap between its Classic and Dense version.

Na

 

[regen1]

Why ?

From IPC targets of Zen 7 Dense wrt Zen 7 Classic shared some months ago.
No need to take it as 100%, just tentative.

 

[StefanR5R]

Apparently, of all the Classic and Dense versions from Zen 4 till Zen 7,
Zen 7 will have the biggest IPC gap between its Classic and Dense version.

Are you referring to instructions per cycle, or to iso-clock performance, or to clock-normalized performance?

(From what AMD published and what has been reproduced by 3rd parties, Zen 4 classic and dense are the same microarchitectures, hence have the same IPC; ditto Zen 5. Naturally, clock-normalized performances of the different SoCs differ.)

 

[Bigos]

The dense versions up till now had less L3 cache per core which could contribute to lower performance per clock. Then, with higher amount of cores for the same IOD it had less bandwidth per core which could also affect it.

Having said that, I have no idea what these Zan 7 classic vs dense "IPC targets" are.

 

[LightningZ71]

Unless AMD makes the decision to make a notable change to the internal compute resources on Zen7 dense as compared to classic, clock normalized performance should be the same for processes contained in L2. I can see a world where the dense cores on Epyc could shift to 256 bit data paths for AVX512, but that's about it.

 

[511]

Unlikely if they can ship full 512bit path on Turin/Venice Dense why they can't do it on Zen7 and A14

 

[LightningZ71]

"can" and "choose to" are different things. If they have large customer interest in super dense processors that aren't AVX512 performance critical, why not?

 

[Josh128]

Apparently, of all the Classic and Dense versions from Zen 4 till Zen 7,
Zen 7 will have the biggest IPC gap between its Classic and Dense version.

Sauce?? That makes no sense as starting with Zen 6, dense has the same cache amounts as classic.

 

[Josh128]

"can" and "choose to" are different things. If they have large customer interest in super dense processors that aren't AVX512 performance critical, why not?

Because its exactly what Intel did and look how that turned out for them.

 

[511]

Intel never disabled AVX-512 in server outside of the atom line which don't have them in the first place except KNL

 

[StefanR5R]

Post #371 speaks of a doubling of L2$ to 2 MB/core in the classic 16c CCD. Perhaps the dense 32c CCD won't get the same L2$ treatment.

Besides cache sizes, there is the question of cache latencies (and bandwidths). I don't think we even have numbers of L3$ latency in the Zen 5c 16c CCD yet, do we?

________
Edit: Somehow I assumed that Zen 7 will have a dense 32c CCD. Zen 6 is supposed to have one, with all cores of the CCD bundled in a single CCX. But Zen 7?

 

[511]

Post #371 speaks of a doubling of L2$ to 2 MB/core in the classic 16c CCD. Perhaps the 32c CCD won't get the same L2$ treatment.

Besides cache sizes, there is the question of cache latencies (and bandwidths). I don't think we even have numbers of L3$ latency in the Zen 5c 16c CCD yet, do we?

No one has micro benchmarked Turin Dense Publicly

 

[regen1]

Are you referring to instructions per cycle, or to iso-clock performance, or to clock-normalized performance?

The latter or what generally is "IPC" or some refer as "PPC" wrt perf/clock.

Sauce?? That makes no sense as starting with Zen 6, dense has the same cache amounts as classic.

Well, this comes from the same "reference" that hinted Intel AMX's future was dead, was getting replaced with something better which was more suitable for both clients and server, which had been posted well before ACE's announcement here:

Advisory Group seems to be working well.
Even before the formation of x86 advisory committee AMD was working on AMX.
Both Intel and AMD should have a successor to AMX already discussed in the committee.
Don't know whether it will be exact same implementation or somewhat different on both sides, also if it would be named the same. The successor should come to both client and server. Guessing Titanlake or later for Intel and Zen7 or later for AMD
Heard AMX development might freeze post DMR, not sure(They perhaps may have it in Silicon further than that for consumer support and there might not be more development/addition inside the AMX instructions???).
Haven't got any definite proof on that yet.


Also this
View attachment 129359It has been redacted since from Intel Docs.

Disclaimer: Some of the above can't be confirmed and some are speculative/hearsay and future plans can change, don't take it as 100%.

Anyway like I said take it as tentative and not 100%. May be something lost in translation or simply wrong(perf instead of IPC?) as well. We will see.

Back then it didn't seem like Zen 7 at launch will use A14, though that can change(could have changed? not sure, don't know. They have time)
Some talks about Zen 7 launching in H2 2029 looks wrong, it's not that late unless something happens/changed drastically.

 

[Joe NYC]

The latter or what generally is "IPC" or some refer as "PPC" wrt perf/clock.


Well, this comes from the same "reference" that hinted Intel AMX's future was dead, was getting replaced with something better which was more suitable for both clients and server, which had been posted well before ACE's announcement here:



Anyway like I said take it as tentative and not 100%. May be something lost in translation or simply wrong(perf instead of IPC?) as well. We will see.

Back then it didn't seem like Zen 7 at launch will use A14, though that can change(could have changed? not sure, don't know. They have time)
Some talks about Zen 7 launching in H2 2029 looks wrong, it's not that late unless something happens/changed drastically.

Are you suggesting that DMR will be the last Intel CPU with AMX and future ones will move to ACE?

If client is both client and server, can it replace NPU on client? Or are the GPUs such as RDNA5 already doing it?

 

[Tuna-Fish]

Because its exactly what Intel did and look how that turned out for them.

AMD is not doing what Intel did. All the cores execute all the same instructions, some of them just take 2 cycles to execute some instructions that the others do in one cycle.

The AMD split AVX-512 implementation is really good! They absolutely should use it in any product where the full avx-512 wouldn't help.

 

[poke01]

ACE?

 

[adroc_thurston]

ACE?

Yup.

 

[Joe NYC]

ACE?

So far, the FAD is 95% history recap and 5% roadmap.

 

[adroc_thurston]

So far, the FAD is 95% history recap and 5% roadmap.

Of course they're gonna do autofellatio, they're winning.

 

[Joe NYC]

Of course they're gonna do autofellatio, they're winning.

A lot of that is going on.

In fairness, some of that is needed, because there is not enough awareness in the industry (financial and other) how far AMD has come.

But as far as roadmap has been extremely vague so far.