Question Zen 6 Speculation Thread

[soresu]

But a lot of times, you gotta compromise.

I know that AVX10 has changed somewhat since Intel's initial announcement, but has APX?

 

[adroc_thurston]

I know that AVX10 has changed somewhat since Intel's initial announcement

Well, they just removed the idiot profiles there.

but has APX?

A few revisions but nothing major.

 

[511]

I know that AVX10 has changed somewhat since Intel's initial announcement, but has APX?

the latest revision is from January

Introducing Intel® Advanced Performance Extensions (Intel® APX)

These extensions expand the x86 instruction set with access to registers and features that improve performance.

www.intel.com

 

[poke01]

Arguing that people don't need faster and more efficient computing is kinda silly don't you think? This isn't like the more cores argument since many high performance required applications and average applications use AVX 512. The disadvantage is only in transistor count in the cpu cores.

that discussion was for client. I said AVX-512 has many benefits in HPC. In client not so much, unless you emulate PS3 games. Most people don’t do that so what do you mean by average applications?

Most average applications don’t even touch AVX2

 

[adroc_thurston]

Most average applications don’t even touch AVX2

Yeah they do.
CPU SIMD is in a funny spot where it's more prolific than you think, but less prolific than SIMD advocates hope it would be.

 

[poke01]

Yeah they do.
CPU SIMD is in a funny spot where it's more prolific than you think, but less prolific than SIMD advocates hope it would be.

I forgot about handbrake and games and whole suite of client professional apps … imm head back to sleep

 

[511]

The issue with AVX-512 is adoption if there is no HW what's the point of writing software for it in client.

 

[coercitiv]

In client not so much, unless you emulate PS3 games.

Ray Tracing Explained

World of Tanks will soon support one of the most cutting-edge rendering technologies.

worldoftanks.com

While we were looking for a way to create soft and realistic shadows on tanks, our long-standing partner, Intel, offered to share their expertise and to assist us. Intel Advanced Rendering engineers helped with high-performance kernels and optimizations. Thanks to concurrent rendering support and the ability to parallelize the rendering we implemented in Update 1.4, the Intel Embree technology was perfect for our game.

It's been said before on the forum, Intel mistakenly used AVX as yet another product segmentation tool. They should have made it ubiquitous across their ecosystem, it would have paid a lot more in the long run.

 

[soresu]

the latest revision is from January

Introducing Intel® Advanced Performance Extensions (Intel® APX)

These extensions expand the x86 instruction set with access to registers and features that improve performance.

www.intel.com

Interesting, I wonder how much back and forth with AMD has affected that.

 

[jpiniero]

It's been said before on the forum, Intel mistakenly used AVX as yet another product segmentation tool. They should have made it ubiquitous across their ecosystem, it would have paid a lot more in the long run.

Celeron and Pentium (and the Atoms) not having AVX should not have prevented AVX adoption.

 

[Covfefe]

Celeron and Pentium (and the Atoms) not having AVX should not have prevented AVX adoption.

It's not just Celerons and Pentiums. It all started with Skylake-X when intel added AVX-512 support in server and HEDT, but not client. In the 9 years since then AVX-512 support has been spotty. They had a few years of AVX-512 support for some of their mobile line-up, (Ice Lake and Tiger Lake iirc), but not desktop. And then they moved to heterogeneous cores in 2021 and won't support it again in client until 2027.

 

[adroc_thurston]

It all started with Skylake-X when intel added AVX-512 support in server and HEDT, but not client

Client didn't have it.
Cannonlake did. Alas.

 

[MS_AT]

So how do you think, will Zen 6 be a match for CCC? https://chipsandcheese.com/p/embracing-ai-with-claudes-c-compiler 😉

 

[gdansk]

So how do you think, will Zen 6 be a match for CCC? https://chipsandcheese.com/p/embracing-ai-with-claudes-c-compiler 😉

Analysts today agree that IPC is more important than performance, and CCC code achieves excellent IPC

Oh that's only a bit of a joke...

 

[Covfefe]

Client didn't have it.

Isn't that what I said?

 

[Hulk]

Yeah they do.
CPU SIMD is in a funny spot where it's more prolific than you think, but less prolific than SIMD advocates hope it would be.

Ah. So that clears it right up. It's pretty good. But not that good.

 

[adroc_thurston]

Ah. So that clears it right up. It's pretty good. But not that good.

Name of the game since the OG SSE, really.

 

[Joe NYC]

So how do you think, will Zen 6 be a match for CCC? https://chipsandcheese.com/p/embracing-ai-with-claudes-c-compiler 😉

 

[DrMrLordX]

Yes, but it is compatible with AVX512. It simply expanded the instructions to be many different bits wide so that the Intel little cores can still execute the instructions without the larger transistor budget. Still, the BEST way to execute AVX 10 is by supporting a 512bit wide AVX instruction and data path.

The issue with AVX-512 is adoption if there is no HW what's the point of writing software for it in client.

The reason why I brought up AVX10 specifically is that you should be able to support 128b, 256b, and 512b instruction/data paths with one codebase. You really had to go out of your way to support AVX-512 which is something most developers were not prepared to do, especially when it was largely absent from client CPUs for a long time.

 

[MS_AT]

The reason why I brought up AVX10 specifically is that you should be able to support 128b, 256b, and 512b instruction/data paths with one codebase.

From practical point of view you can do that with AVX512, as only Xeon Phi does not support 128b/256b AVX512 extension afaik. Yes you need to check one more flag for dynamic dispatch compared to AVX10 but I would say that's hardly a problem.

You anyway need to have explicit kernels for 128b/256b/512b instruction usage if for one reason or another use of masking would not be appropriate regardless if it is AVX512+extensions or AVX10.

 

[adroc_thurston]

The reason why I brought up AVX10 specifically is that you should be able to support 128b, 256b, and 512b instruction/data paths with one codebase

No, that is desd.
AVX10 is 512b only.

 

[OneEng2]

The reason why I brought up AVX10 specifically is that you should be able to support 128b, 256b, and 512b instruction/data paths with one codebase. You really had to go out of your way to support AVX-512 which is something most developers were not prepared to do, especially when it was largely absent from client CPUs for a long time.

I think that Intel is using AVX10 as a way of mitigating their huge losses against AMD where AVX512 is being utilized. I suspect they had to think long and hard about how to make an instruction set that allowed MUCH smaller transistor budgets to exist in their little cores, but still perform the same code operations .... just much slower.

Correct me if I am incorrect, but all you have to do to get AVX-512 support is use a compiler that supports it. Then it gets used if the hardware exists to use it. I suspect it is pretty uniform by now.

No, that is desd.
AVX10 is 512b only.

Since I know that adroc will never actually support his own assertions, could someone else please explain to me with links if this is or is not true? Last time I dove in, this was blatantly NOT true.

 

[511]

Since I know that adroc will never actually support his own assertions, could someone else please explain to me with links if this is or is not true? Last time I dove in, this was blatantly NOT true.

here is the latest AVX 10 spec

Intel® Advanced Vector Extensions 10.2 (Intel® AVX10.2) Architecture Specification

This document describes the Intel® Advanced Vector Extensions 10.2 Instruction Set Architecture.

www.intel.com

also this

Intel AVX10 Drops Optional 512-bit: No AVX10 256-bit Only E-Cores In The Future - Phoronix

www.phoronix.com

 

[Nothingness]

Since I know that adroc will never actually support his own assertions, could someone else please explain to me with links if this is or is not true? Last time I dove in, this was blatantly NOT true.

It will support operations on VL of 128, 256 and 512 bits. Previously the spec stated that 512-bit was optional; it is now mandatory. This is perhaps what @adroc_thurston meant.