Question Zen 6 Speculation Thread

[Joe NYC]

So dense has the same L3/core as classic this time, instead of half?

I wonder what the difference is size is between the classic and dense then.

Not only that, but with

32 cores * 4 MB = 128 MB

The size of the L3 pool goes up, which allows the active cores that use a lot of memory to get even bigger allocation of that L3. The size of the L3 pool goes up 4x from Turin Dense to Venice dense.

 

[Joe NYC]

SP7 then

Zen 7 then

 

[Tuna-Fish]

you do not want either of those for per-C licensing.
you want a 32 or 48c fmax part.

Or even less cores. There are EPYCs with 1 enabled core per CCD, they are popular for this crowd.

 

[Joe NYC]

you do not want either of those for per-C licensing.
you want a 32 or 48c fmax part.

I think, better than 50% probability that AMD comes back with V-Cache for the Zen 6 classic, for highest single core performance.

 

[adroc_thurston]

Or even less cores. There are EPYCs with 1 enabled core per CCD, they are popular for this crowd.

Kind of, you're not winning much freq from going to 16c.

I think, better than 50% probability that AMD comes back with V-Cache for the Zen 6 classic, for highest single core performance.

V$ is completely irrelevant for fmax SKUs.
It's completely irrelevant in server outside of specific HPC workloads.

 

[Tuna-Fish]

Kind of, you're not winning much freq from going to 16c.

The main purpose being to push core counts down because Oracle doesn't accept "sure we have 32 but we are only using 16 of them".

It's completely irrelevant in server outside of specific HPC workloads.

If you can fit some of your most important indexes in cache, it suddenly becomes very relevant for databases.

 

[adroc_thurston]

The main purpose being to push core counts down because Oracle doesn't accept "sure we have 32 but we are only using 16 of them".

World's ain't ending on Oracle.

If you can fit some of your most important indexes in cache, it suddenly becomes very relevant for databases.

Niche and hard to execute on.
So far main V$ usecases in DC are down to carefully MPI-sliced HPC workloads.
That's why Turin-X went the way of the dodo.

 

[Joe NYC]

The main purpose being to push core counts down because Oracle doesn't accept "sure we have 32 but we are only using 16 of them".

If you can fit some of your most important indexes in cache, it suddenly becomes very relevant for databases.

One of the benefits of F CPUs with reduced core count per CCD was increased L3 per CCD. With Genoa-X, V-Cache on top of the CPU was still slowing down the FMax.

The new options on the table for Zen 6 with V-Cache:
- also increase L3 per core
- but don't reduce FMax
So both can be done without wasting precious N2 die by disabling perfectly fine cores.

 

[Joe NYC]

BTW, does anyone know which version of Venice is being use in Helios rack scale installation? 256 core dense or 96 core classic?

 

[Saylick]

BTW, does anyone know which version of Venice is being use in Helios rack scale installation? 256 core dense or 96 core classic?

Total guess, but probably the 96 core classic? For reference, Vera is a 88 core CPU, also with SMT.

 

[adroc_thurston]

With Genoa-X, V-Cache on top of the CPU was still slowing down the FMax.

The new options on the table for Zen 6 with V-Cache:
- also increase L3 per core
- but don't reduce FMax
So both can be done without wasting precious N2 die by disabling perfectly fine cores.

just forget about the V$.

For reference, Vera is a 88 core CPU, also with SMT.

We don't care what NV does, server Tegras are poo poo.

 

[lucasworais]

Does anyone have some market research to prove this theory?

No. We are speculating here.

 

[Joe NYC]

We don't care what NV does, server Tegras are poo poo.

So, you think it will be 256 core Venice Dense in those Helios nodes?

 

[adroc_thurston]

So, you think it will be 256 core Venice Dense in those Helios nodes?

Probably.
You want fat membw for offloading host-specific functions.

 

[Abwx]

Or even less cores. There are EPYCs with 1 enabled core per CCD, they are popular for this crowd.

Seems that it is 4 cores per CCD with 8 chiplets and 32 cores.

 

[Joe NYC]

Probably.
You want fat membw for offloading host-specific functions.

Looks like 1 CPU per node from Dylan Patel picture:

https://twitter.com/x/status/1923143004715614294

 

[adroc_thurston]

Looks like 1 CPU per node from Dylan Patel picture:

I know what it is; you don't have to quote dolan to me either.