Question Zen 6 Speculation Thread

[adroc_thurston]

You can do 24ch 1DPC.

That makes 2p really hard, also where do I scourge for all the shoreline necessary for 24 channels of DDR5.

 

[511]

That makes 2p really hard, also where do I scourge for all the shoreline necessary for 24 channels of DDR5.

Do you need 2P with 512C/1024T? Gor DIMM Shoreline 8 Channel on 3 Sides of socket

 

[adroc_thurston]

Do you need 2P with 512C/1024T?

It's the standard option really.

Gor DIMM Shoreline 8 Channel on 3 Sides of socket

Hatcheting PCIe further is unwise.
In any case, that's the futureworld problems.

 

[Markfw]

Do you need 2P with 512C/1024T? Gor DIMM Shoreline 8 Channel on 3 Sides of socket

well, I certainly love my 9755 128 core beasts.

 

[511]

With DMR getting a 4 Socket System 🤣 we will have 1024 real Cores in 4S.

 

[blackangus]

Well there is speculation - Something based on known information.

As usual, your attempt to define the world according to your own definition is .... wrong.

Dictionary Definition

Speculation: "The forming of a theory or conjecture without firm evidence."

Not only are you wrong, you are 180 degrees wrong. Speculation, by its very definition, is a theory that has no proof or "known information".

Now, your "speculation" on why we won't see core counts go out the ceiling (RAM per core, or bandwidth per core) may have merit in some situations, but not all.

A productive speculation would be to outline what instances more cores without more RAM or more bandwidth is useful.

Also, as others have done, outlining the cost to AMD to increase core count on A14/A16 is an interesting topic for speculation .... and which node Zen 7 might be on in the future.

I don't consider 512 cores per socket to be out of the realm of possibility for AMD.... although as things sit today, it may well be outside the realm of financial good sense.

1. I think you have attacked the wrong guy with your "As usual..." because I rarely post here and even more rarely argue.
2. The definition you posted and what I said are not mutually exclusive as you imply. There is a term "Baseless Speculation"... which is the difference I am describing.
3. Everything after this clearly shows you quoted the wrong person, as I haven't said anything you posted...

Also theory by definition is based on some known information. You don't get to be a theory until you have some supporting fact to draw a solid line of conclusion. (This is of course the proper scientific usage of the word theory)

https://www.merriam-webster.com/dictionary/theory
The Difference Between Hypothesis and Theory
A hypothesis is an assumption, an idea that is proposed for the sake of argument so that it can be tested to see if it might be true.
In the scientific method, the hypothesis is constructed before any applicable research has been done, apart from a basic background review. You ask a question, read up on what has been studied before, and then form a hypothesis.

A hypothesis is usually tentative; it's an assumption or suggestion made strictly for the objective of being tested.
A theory, in contrast, is a principle that has been formed as an attempt to explain things that have already been substantiated by data.

 

[DrMrLordX]

Naa, speculation implies understanding the limits of what's possible instead of going "512c sockets are viable rn because IPHONE PRO MAX you see".

To be perfectly honest, I just found the phraseology to be amusing and decided that even the stuff that may be possible might still qualify as "nerdwank".

 

[OneEng2]

It's not competition 512C just doesn't make sense with the density gains you have to significantly increase both your package size and need more Bandwidth to feed the beast.

Normally, I would agree; however, in DC it is my THEORY that the margins justify expense and therefore the upper limit of how big a die will be is only limited by physics and existing machines since nearly any cost can be born as long as it results in AMD retaining the market in this highly profitable segment.

Now, I am not of the opinion that Zen 7 will be in a position where such radical actions will be needed by AMD in order to retain their dominant market position.

So my speculation is that we will not see a 512c part for Zen 7.

 

[LightningZ71]

Whatever happened to CXL attached RAM? 5th Gen EPYC fully supports the technology and has even partnered with Micron for compatible modules. There's really not a "limit" for total system RAM imposed by the 12-16 channel shoreline limitation, just that you have to pay a smallish price in latency and bandwidth (still massively faster than SSD) for the CXL ram...

 

[Joe NYC]

MLID says not a "Bunch of Wires" but a silicon bridge made by UMC, also specifies packaging company (not TSMC).

 

[511]

 

[adroc_thurston]

MLID says not a "Bunch of Wires" but a silicon bridge made by UMC

It's the same thing.
BoW is an interface style.

 

[reaperrr3]

Normally, I would agree; however, in DC it is my THEORY that the margins justify expense and therefore the upper limit of how big a die will be is only limited by physics and existing machines since nearly any cost can be born as long as it results in AMD retaining the market in this highly profitable segment.

Now, I am not of the opinion that Zen 7 will be in a position where such radical actions will be needed by AMD in order to retain their dominant market position.

So my speculation is that we will not see a 512c part for Zen 7.

Rumors so far suggest 264 cores, instead of Venice-D's 256, which seems believable to me precisely because the figure is so modest.

In my opinion, that points to a layout change of the dense server CCD, from 2 rows of 16 cores to a 3x11 layout.
Since there's also rumors that the L3 is wandering outside the CCD, that's not so far-fetched.

Architecturally, Zen7 is allegedly the next proper tock, with rumored 15-25% IPC uplift, which would require a substantial of additional logic transistors, probably eating up most or all the power- and transistor budget freed up by the A14 shrink, so a tiny core count bump makes sense in that regard, too.

 

[adroc_thurston]

In my opinion, that points to a layout change of the dense server CCD, from 2 rows of 16 cores to a 3x11 layout

Venice is a 4*8 mesh.
What?

 

[Kaffeekenan]

Venice is a 4*8 mesh.
What?

He talks about Zen 7. Hence the 3 times 11 core arrangement.

 

[adroc_thurston]

He talks about Zen 7. Hence the 3 times 11 core arrangement.

It's not 3*11 either for Zen7.

 

[Kaffeekenan]

It's not 3*11 either for Zen7.

At least MLID said that. So what is it then?

 

[adroc_thurston]

So what is it then?

No one knows because core counts have not been frozen.

 

[Kaffeekenan]

No one knows because core counts have not been frozen.

If noone knows, then how can you say "It's not 3*11 either for Zen7". Does not really make sense.

 

[poke01]

If noone knows, then how can you say "It's not 3*11 either for Zen7". Does not really make sense.

Because they have not been selected.

 

[poke01]

Here’s a rule I’ll follow from on, I don’t watch or read the content of anyone who comes on MILD YouTube channel.

Those people are just promoting that grifter. Seriously, I miss Anandtech.


People like HUB, Kit, level1tech, are just promoting him and his way of conducting business. You’ve seen that’s guys influence already on these stupid tech sites that publish anything

 

[inquiss]

If noone knows, then how can you say "It's not 3*11 either for Zen7". Does not really make sense.

It could end up being the case, but right now it's not the case. It does make sense.

 

[adroc_thurston]

If noone knows, then how can you say "It's not 3*11 either for Zen7". Does not really make sense.

It means configs ain't frozen.
Which they ain't, AMD picks one basically right before the TO.

 

[basix]

It could end up being the case, but right now it's not the case. It does make sense.

He said "it's not 3x11" and "nobody knows" and "it's not finalized". So when nobody knows what it will be, why more or less excluding 3x11 with a rather firm statement? This just doesn't hold under logical scrutiny. It still can turn out to be a 3x11 chiplet. It is just not sure yet.

If he would have phrased it like "it will probably not be a 3x11 arrangement because of XY or YZ is more likely" it would have sounded different. It's not what you say, but how you say it.

But anyways. We probably can agree that multiple options are on the table, when you are doing stacked L3-Cache and have a 2D-Arrangement of your cores and stacked cache tiles. And we probably also agree, that the sum of all cores will be >=32C, because Zen 6 already brings a 32C chiplet / CCX:

• 4 x 8
• 3 x 11
• 3 x 12
• 4 x 9
• 4 x 10
• 4 x 11
• 4 x 12
• 3 x 16
• ...

AMD will pick the one which delivers the best compromise of being technically good, well manufacturable and delivers what the market wants.

Personally, I somehow like a 3x wide chiplet. The main reason for this is IOD beachfront. If you have a wide chiplet, you run out of space to attach it to the IOD.
Turin with the 16C chiplets shows something similar. It will be interesting, how the 32C chiplet of Zen 6 is arranged. It will be either 4x8 or 2x16.
The latter makes more sense to me, if you are still having L3-Cache (and at the same time with doubled capacity per core) in the middle. Otherwise the CCD gets rather wide.
A 3 x 16 CCD for Zen 7 would be a natural evolution of that. Keep the 16C length and replace the middle row L3-Cache with an additional row of CPU cores.
With 3 x 11 you could shorten the CCD and make it smaller and cheaper for many use cases. And potentially open up the way for CCD daisy chaining (where too long single CCDs are not optimal).

Not that 3x rows are mandatory for achieving rectangular, "high aspect ratio" CCDs. There are two potential workarounds:

• You can change the aspect ratio of the CPU core itself to account for CCD width
  • But it still seems to be ideal to have an as square as possible core, with L2-Cache and FPU attached to its sides, making it rectangular in shape
  • As Zen 7 is speculated to double L2$ capacity, it would result in an even higher aspect ratio
  • But Intel did some fancy cache arrangement with Skylake, packing large L3$ cache portions to the side of the core. Zen 7 could do something similar for its L2$.
• If your core is rectangular, you could rotate it so that the shorter side faces towards the IOD
  • With that you could make 8C groups resembling todays Zen 5 CCX layout, but without the L3$ in the middle but 3D stacked

 

[inquiss]

He said "it's not 3x11" and "nobody knows" and "it's not finalized". So when nobody knows what it will be, why more or less excluding 3x11 with a rather firm statement? This just doesn't hold under logical scrutiny. It still can turn out to be a 3x11 chiplet. It is just not sure yet.

If he would have phrased it like "it will probably not be a 3x11 arrangement because of XY or YZ is more likely" it would have sounded different. It's not what you say, but how you say it.

But anyways. We probably can agree that multiple options are on the table, when you are doing stacked L3-Cache and have a 2D-Arrangement of your cores and stacked cache tiles. And we probably also agree, that the sum of all cores will be >=32C, because Zen 6 already brings a 32C chiplet / CCX:

• 4 x 8
• 3 x 11
• 3 x 12
• 4 x 9
• 4 x 10
• 4 x 11
• 4 x 12
• 3 x 16
• ...

AMD will pick the one which delivers the best compromise of being technically good, well manufacturable and delivers what the market wants.

Personally, I somehow like a 3x wide chiplet. The main reason for this is IOD beachfront. If you have a wide chiplet, you run out of space to attach it to the IOD.
Turin with the 16C chiplets shows something similar. It will be interesting, how the 32C chiplet of Zen 6 is arranged. It will be either 4x8 or 2x16.
The latter makes more sense to me, if you are still having L3-Cache (and at the same time with doubled capacity per core) in the middle. Otherwise the CCD gets rather wide.
A 3 x 16 CCD for Zen 7 would be a natural evolution of that. Keep the 16C length and replace the middle row L3-Cache with an additional row of CPU cores.
With 3 x 11 you could shorten the CCD and make it smaller and cheaper for many use cases. And potentially open up the way for CCD daisy chaining (where too long single CCDs are not optimal).

Not that 3x rows are mandatory for achieving rectangular, "high aspect ratio" CCDs. There are two potential workarounds:

• You can change the aspect ratio of the CPU core itself to account for CCD width
  • But it still seems to be ideal to have an as square as possible core, with L2-Cache and FPU attached to its sides, making it rectangular in shape
  • As Zen 7 is speculated to double L2$ capacity, it would result in an even higher aspect ratio
  • But Intel did some fancy cache arrangement with Skylake, packing large L3$ cache portions to the side of the core. Zen 7 could do something similar for its L2$.
• If your core is rectangular, you could rotate it so that the shorter side faces towards the IOD
  • With that you could make 8C groups resembling todays Zen 5 CCX layout, but without the L3$ in the middle but 3D stacked

It's quite simple. It's not 3x11 because it's not anything. No logic was broken in this statement.