Question Zen 6 Speculation Thread

[adroc_thurston]

That is a very interesting idea, indeed. For Zen 6 I do not expect something like that to happen. For Zen 7 I think not as well (16/33C CCDs, bigger L3$ and simply faster cores are already a decent enough update). But Zen 7 could still introduce it (core count mania). Would be sick to see a 512C Zen 7 SKU

As the beachfront of the IOD is limited, daisy-chaining makes very much sense in the mid- to longterm. It are just a few hundred of GByte/s if putting 2x CCDs in series. Such a concept opens up the door to very huge core count scalings without adding too much cost (much bigger CCDs, much more IOD area, ...).

a) this is nonsense
b) no one wants 512c sockets since DRAM pop gets nightmarishly hard.

512C totally doubt this with the meager density gains they have to make the package significantly larger 384C seems possible

No one wants either, not with modern DRAM densities anyway.

 

[511]

No one wants either, not with modern DRAM densities anyway.

Kind of expected tbh DRAM don't have mem bandwidth for 512 Cores in 3-4 years

 

[adroc_thurston]

Kind of expected tbh DRAM don't have mem bandwidth for 512 Cores in 3-4 years

Oh I ain't even talking bandwidth.
Capacity!
You really want a ratio of DRAM capacity per core to get a VM farm going.

 

[511]

You really want a ratio of DRAM capacity per core to get a VM farm going.

24 Channel DRAM /s

 

[LightningZ71]

Eh, they've got PCIe 5.0 on consumer boards now. They could implement CXL over 5.0 to a RAM expansion card on board any time they want to. While it wouldn't be super fast, it would certainly be quick enough to be useful.

But I don't see that happening anytime soon as it would gut the workstation market.

 

[ToTTenTranz]

Eh, they've got PCIe 5.0 on consumer boards now. They could implement CXL over 5.0 to a RAM expansion card on board any time they want to. While it wouldn't be super fast, it would certainly be quick enough to be useful.

But I don't see that happening anytime soon as it would gut the workstation market.

Perhaps not with PCIe 5.0 yet, but come the PAM4 evolutions they should be able to make usable PCIe RAM sticks, as long as the applications are latency-tolerant.

 

[Josh128]

a) this is nonsense
b) no one wants 512c sockets since DRAM pop gets nightmarishly hard.

No one wants either, not with modern DRAM densities anyway.

This race to spam core count on CPUs is excruciating. After 2nm, we need something more interesting, like optical logic or quantum integration in the processor. Seems we are hitting the wall.

 

[mmaenpaa]

You have AMD's GAIA and Intel's OpenVINO that can integrate Ollama. Both can get you to use an NPU for running LLMs on Windows, with which you can also make agents.

If you're willing to dedicate a couple of hours to set this up, you can get a NPU to run LLMs for you locally with a lower power consumption compared to running it on the iGPU.


EDIT: even easier than using OpenVINO, Intel has the AI Playground app that also makes use of its NPUs:

Introducing AI Playground – Intel Gaming Access

game.intel.com

Check out a demo of the app here, at the timestamp:

You could try to implement a local running LLM to work on Outlook and Word, it's supposedly possible.. but IIRC it's not easy. Microsoft isn't super interested in letting people off the hook on paying $30/month for the full Copilot M365 experience.

Thanks,

This looks interesting. Actually I am paying that 30€ for Copilot & 20€ for Chatgpt+. I was hoping to find a shortcut to finally arrange family photos on my laptop🤣

 

[basix]

512C totally doubt this with the meager density gains they have to make the package significantly larger 384C seems possible

Such a CPU would simply get bigger and more expensive. Density gains are not relevant

When Zen 7 should bring stacked L3-Caches across the board, the CCDs should get smaller. Package area will also not be a limiting factor.

a) this is nonsense
b) no one wants 512c sockets since DRAM pop gets nightmarishly hard.

No one wants either, not with modern DRAM densities anyway.

Not all applications are memory bandwidth and/or capacity limited. There would be a market for that.

• Zen 7 is rumored to bring 7MB L3$ and 2MB L2$ per core. That should reduce bandwith pressure. And some V-Cache variants might be there as well.
• Then the possibility for LPDDR6 with LPCAMM2: With 17'033 MT/s and 16-channel width we get 3.2 TByte/s of bandwidth. Or 6.4 GByt/s per core. This is very similar to Zen 5 SKUs (same as 6400 MT/s DDR5 with 12-ch on a 96C EPYC).
• Regarding memory capacity: 8 TByte results in 16 GByte per core. That seems to be enough for many applications. Zen 5 EPYC already supports up to 9 TByte but as far as I know, most installments use something in the 0.5...2.0 TByte range per socket.

I do not see technical problems at all. The only challenge could be cost for all that. But it is maybe still cheaper to have one super huge CPU instead of two with halved cores and memory. The only setback is memory bandwidth, where a dual-socket system totals more.

 

[511]

Such a CPU would simply get bigger and more expensive. Density gains are not relevant

When Zen 7 should bring stacked L3-Caches across the board, the CCDs should get smaller. Package area will also not be a limiting factor.

And how about feeding this beast at best it will be 384C CPU sometime in 2028-29.

 

[basix]

See my answer to adroc

 

[511]

It would easily be 1000W+ . DMR is doing stacked L3 Cache and L3 is never per core it's shared L3 can be per stop though.

 

[basix]

And? Did you miss the 1000W+ cooling solution demos?

https://twitter.com/x/status/1960886604832391526

DMR is doing stacked L3 Cache and L3 is never per core it's shared L3 can be per stop though.

It is clear that L3 cache gets shared. 7MB/core instead of 4MB/core is just an indication that you have more L3$ capacity to use. And that helps to reduce bandwidth pressure.

 

[adroc_thurston]

This race to spam core count on CPUs is excruciating

We ain't doing that.

Not all applications are memory bandwidth and/or capacity limited.

Yeah they are.

Then the possibility for LPDDR6 with LPCAMM2: With 17'033 MT/s and 16-channel width we get 3.2 TByte/s of bandwidth. Or 6.4 GByt/s per core. This is very similar to Zen 5 SKUs (same as 6400 MT/s DDR5 with 12-ch on a 96C EPYC).

This is a naively optimistic assumption of DRAM speed scaling.
like dawg LP6 starts at 10.6GT/s. It's not very fast.

Regarding memory capacity: 8 TByte results in 16 GByte per core

The only way you're getting 8TB@skt on a 16ch platform is by using expensive ass 3DS LRDIMMs aka good luck fitting into your cost-per-rack target.

All you've said is just hypothetical nerd wank; has nothing to do with how the world works at large.

 

[Darkmont]

You’re off your rocker if you think we’re getting 17 Gbps per pin on a socketable connector in 2028 with LPDDR6. Be lucky to get 14.4 thereabouts and certainly nowhere near hyperscaler lands. Not even accounting for DDR being the memory of choice in server because it’s MADE for it. And that all the blades in the world are designed to accommodate DIMMs and cool them

 

[adroc_thurston]

Be lucky to get 14.4 thereabouts

Even that is horribly optimistic outside of the MoP/PoP ghetto

 

[basix]

Just as a side note:
Turin 192C has 3.2 GB/s per core with DDR5-6400. Normal DDR6 DIMMs (16-channel) with 12.8 Gbps would match that in case of 512 cores. Slowest 16-channel 10.67 Gbps LPDDR6 would exceed that (4.0 GB/s per core). And Zen 7 is earliest an end of 2027 product.

Or in other words:
512C could happen, if there are customers who want that from AMD. Technology will not prevent that from happening.

 

[adroc_thurston]

Turin 192C has 3.2 GB/s per core with DDR5-6400

yeah that sucks balls. Next.

Or in other words: Slowest 16-channel 10.67 Gbps LPDDR6 would exceed that in case of 512 cores (4.0 GB/s per core)

Again, no one wants 512c sockets.
Just stop.

 

[Doug S]

yeah that sucks balls. Next.

Again, no one wants 512c sockets.
Just stop.

Pretty sure people like you 10 years ago were saying no one wants 64c sockets, and 20 years ago no one wants 8c sockets. What sounds crazy today becomes normalized over time as technology evolves to support it. When Apple shipped the first iPhones its massive 3.5" screen and the overall phone itself seemed ridiculously large - after all the past 20 years of cell phone evolution had been all about making phones smaller, not bigger! There were persistent rumors the first few years about an "iPhone Mini" that would be the size of an iPod Nano, for people who just wanted to use it as a phone and music player, and thought browsing and apps on your phone was a gimmick or niche market.

Around 2010 or so no name Chinese companies starting making phones with 4.5" and even 5" screens and there were pictures posted on social media and everyone laughed and laughed at how ridiculous they looked when people were holding them to their ear. Then Samsung started making phones that size, people realized why Chinese people were going crazy for them, and before long everyone was like "when is Apple going to introduce larger phones!?" Now we're pushing 7", 4x the area of those first iPhones.

What would people have thought about a Pro Max if you showed them a picture of it in 2010, with the humongous screen and all those cameras sticking out the back. What possible use could there be for THREE cameras? What do you mean there are two more on the front???

 

[adroc_thurston]

Pretty sure people like you 10 years ago were saying no one wants 64c sockets

DRAM scaled.

and 20 years ago no one wants 8c sockets.

DRAM SCALED

When Apple shipped the first iPhones its massive 3.5" screen and the overall phone itself seemed ridiculously large - after all the past 20 years of cell phone evolution had been all about making phones smaller, not bigger! There were persistent rumors the first few years about an "iPhone Mini" that would be the size of an iPod Nano, for people who just wanted to use it as a phone and music player, and thought browsing and apps on your phone was a gimmick or niche market.

Around 2010 or so no name Chinese companies starting making phones with 4.5" and even 5" screens and there were pictures posted on social media and everyone laughed and laughed at how ridiculous they looked when people were holding them to their ear. Then Samsung started making phones that size, people realized why Chinese people were going crazy for them, and before long everyone was like "when is Apple going to introduce larger phones!?" Now we're pushing 7", 4x the area of those first iPhones.

What would people have thought about a Pro Max if you showed them a picture of it in 2010, with the humongous screen and all those cameras sticking out the back. What possible use could there be for THREE cameras? What do you mean there are two more on the front???

that's very wordcel of you, but no, there is no PRO MAX Inspur server that does anything PRO MAXXIER than any OEM server did in 2007.

 

[igor_kavinski]

Don't really think it's a leak but what do I know?

 

[Doug S]

DRAM scaled.

Maybe you need to look at per core memory bandwidth trends over time if you think the generous amounts of bandwidth we have today are a requirement. Hint: not all applications place the same demands on memory bandwidth.

 

[adroc_thurston]

Maybe you need to look at per core memory bandwidth trends over time if you think the generous amounts of bandwidth we have today are a requirement. Hint: not all applications place the same demands on memory bandwidth.

not bandwidth ffs, capacity.
Omegafat sockets need a ton of DRAM (as in actual DRAM bits) to be useful!

 

[igor_kavinski]

Omegafat sockets need a ton of DRAM (as in actual DRAM bits) to be useful!

Not when the cores are working with a lot of shared data.

 

[adroc_thurston]

Not when the cores are working with a lot of shared data.

That's not how modern virtualized or containerized deployments work and definitely not how CSP favelas work!