marees
Platinum Member
Imagine the RDNA 5 version of 3060 12gb could be a 10050xt 64gb !!
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Question Zen 6 Speculation Thread
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AMD could be trolling NVidia on low end with big LPDDR5 memory sizes.
What I wonder though, why not doe the same throughout the stack?
If NVidia can go up to 512 bit memory bus (8 channels) why not go to 6 LPDDR6 channels with high end card, which would be 576 bits?
Because then, if the biggest LPDDR5 memory chip is 64 GB, the high end professional / AI card could have 384 GB, which would be maximum trolling.
Or maybe split high end gaming to use GDDR7 and high end professional / AI with LPDDR6.
But, it's also good to keep in mind that NVidia is also doing a lot of work with LPDDR across the product stack, so AMD may not have a monopoly here.
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I don't deny it. But I guess you don't hit peak bandwidth. At least I don't when compiling llvm with llvm on Windows, which I guess is somewhat comparable load to Unreal. Plus looking at various tests from phoronix compilation does not really scale well with memory bandwidth. https://www.phoronix.com/review/threadripper-9000-ddr5-6400-4800/2 https://www.phoronix.com/review/amd-ryzen9-9950x-ddr5/4 https://www.phoronix.com/review/8-12-channel-epyc-9005/4 (the compilation benchmarks are usually in the middle of the page).
Or maybe it would be better to say that once you satisfy a specific BW threshold (likely related to how many cores you have and how much parallelism exists in the build), compilation workload does not care anymore and the BW requirement is relatively modest in the first place.
blackangus
Senior member
I'd GUESS that compilation in both cases is memory ops bound rather than bandwidth bound. But that is just a guess.
MrMPFR
Senior member
Cost saving measures right?
NPU + GPU vs GPU only but beefed up ML HW = higher TOPS/mm^2.
Imagination Technologies also deprecating NPU with e-series GPU.
Navi 48 MALL has around 10% area overhead. IDK how much area L2+MALL unification (matching NVIDIA L2) adds vs L2 only.
AMD clearly going the NVIDIA route with no MALL in RDNA 5. Look at how NVIDIA's GB203 can squeeze all non-shader GPU core logic into a area footprint only ~10% higher than Navi 48. Obviously different µarch, but Navi 48 could've been significantly smaller with 64MB L2 instead of 8MB L2 + 64MB MALL.
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MrMPFR
Senior member
What is GMD and AID?
SED = Shader Engine Die
MID = Media Interface Die
GMD = ?
AID = ?
GFX13 and later introduces SE autonomy (L1 cache) so could MALL could effectively be L2 in actual chiplet designs? Just can't see why SED chiplets requires one more cache level when SEs are almost completely autonomous in GFX13 and later. Unless AMD is clustering SEs and need a local larger datastore than L1's within SEs. Makes sense as IIRC one RDNA 4 SE is only ~26-27mm^2.
This assumes SEs aren't completely rearchitected and blown up to massive size with RDNA 6 and later (RDNA 5 isn't going full MCM). Do we even know anything about RDNA 6 rn?
Maybe UDNA is about laying groundwork for heterogenous compute in GFX14+? Hypothetically mixing and matching CDNAx, RDNAx, and ASIC chiplets with one frontend (OS only sees one GPU). Effectively a Zen-like GPU chiplet architecture.
Maybe a few tidbits at AMD's 2025 Financial Analyst day in November?
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ToTTenTranz
Senior member
I guess Medusa Halo Mini is the actual Strix Point successor to go into handhelds and small gaming laptops.
128bit LP5X might be a bottleneck, but LP6 would be a big improvement.
AMD going with LPDDR for their dGPUs sounds crazy, though. How is pJ-per-byte for LP6 compared to GDDR7?
It does lend to very high memory capacities that many will be looking for running AI models locally.
That's probally just MLID being MLID.
marees
Platinum Member
If true then medusa (mini) premium will also go into 2027 version of Xbox rog Ally handhelds
ToTTenTranz
Senior member
And Sony's rumored "PS6 handheld" gets DOA unless it's a third of the price.
If people can play PS4 and PS5 games (plus maybe PS3 and certainly PS1 + 2 emulation on Zen6) on it then it has something other handhelds do not have legally, or without some measure of technical aptitude.
Don't underestimate the draw of off the shelf legacy game libraries.
Given that the more expensive Ally is $899, it'll be more interesting to see how much more any Zen 6 Windows handhelds end up being.
marees
Platinum Member
adroc_thurston
Diamond Member
much much better
Jan Olšan
Senior member
Wow, is that confirmed or just based on them not announcing next XDNA gen (which could change)?
adroc_thurston
Diamond Member
GPU guys just won.
No mention of NPU in upcoming Zen 6 RDNA5 based notebook CPU (from MLID leak).
We can safely assume XDNA3 is happening, they maybe just haven't seen such a positive response from customers to AI features and don't want to make a noise about it.
Jan Olšan
Senior member
That doesn't have to mean anything. USB4 support or Zen 6 cores supporting SMT also was not mentioned there.
There ist that 50 TOPS requirement for Windows Copilot. With 8 CU at 3 GHz and RDNA4 style INT8 / FP8 matrix acceleration you are right there. And who knows, maybe does AMD double matrix FLOPS per CU on RDNA5 (but I doubt it).
50 TOPS would then be some interesting point on Zen 6 desktop. NPU or some beefed up iGPU?
50 TOPS would then be some interesting point on Zen 6 desktop. NPU or some beefed up iGPU?
adroc_thurston
Diamond Member
Yeah but GPU guys won.
all hail gfx13.
There may be a set of transitional SKUs that may still be using RDNA 3.5, still be supporting LPDDR5, still have NPU in 2026.
This roadmap points to late 2026 to 2027, with RDNA5 and it seems like no longer NPU present.
Saylick
Diamond Member
Which is good. The NPU was used for one thing only, and was wasted sand otherwise.
Honestly I've come around on the AMD NPUs, they're great dataflow accelerators when used for non-AI tasks, even if the focus on low precision datatypes looks kind of annoying when trying to get the full performance out of them for other purposes.
But generally the architecture and hardware is fascinating and looks very capable, even if using them for general purpose tasks is entirely underexplored IMO and likely will remain that way if they do get abandoned.
(Think of them as a non-graphics GPU with less flexible compute scheduling (cores don't change what code they're executing on the fly) but able to utilize some of the routing and spatial optimization tricks you normally see in FPGAs to shuffle data around more efficiently)
That said, I'd not be suprised at all if they end up replaced by more capable graphics hardware considering the die space they occupy and the fact that people actually do program for GPUs already, which can do many of the same things even if not always quite as good, and do a lot of other things better.
But generally the architecture and hardware is fascinating and looks very capable, even if using them for general purpose tasks is entirely underexplored IMO and likely will remain that way if they do get abandoned.
(Think of them as a non-graphics GPU with less flexible compute scheduling (cores don't change what code they're executing on the fly) but able to utilize some of the routing and spatial optimization tricks you normally see in FPGAs to shuffle data around more efficiently)
That said, I'd not be suprised at all if they end up replaced by more capable graphics hardware considering the die space they occupy and the fact that people actually do program for GPUs already, which can do many of the same things even if not always quite as good, and do a lot of other things better.
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