Question Zen 6 Speculation Thread

[fastandfurious6]

RDNA5 will probably not make it into most of the Zen 6 products except maybe Medusa Halo.

I guess the whole creation process doesn't allow for early RDNA5 beta and then the full version right lol

also there's no real benefits for APU to have rdna5 if you use dgpu anyway right

Halo is the main product where it rly matters

 

[Kepler_L2]

MALL will still be used in 3D/chiplet parts right?

For actual chiplet stuff (SED+AID+MID) I think so, but for the quasi-monolithic GPUs like ATx with just GMD+MID it's gone.

 

[Joe NYC]

I guess the whole creation process doesn't allow for early RDNA5 beta and then the full version right lol

also there's no real benefits for APU to have rdna5 if you use dgpu anyway right

Halo is the main product where it rly matters

RDNA5 iGPU could matter in other SKUs if RDNA5 iGPU could take on full responsibilities of NPU and NPU is removed from the die.

 

[OneEng2]

Intel won't drop a 52 core onto the desktop. That 52 core will go in a server, which AMD will eat for lunch.

I thought that Intel was going to make a dual CCD desktop version (like AMD) having CCD's with 8P and 16E cores and the IOD having 4 LPE cores.

While it has been my contention that anyone that would benefit from that many cores would likely pick a Threadripper which would "eat it for lunch".

Since Zen 3, AMD's been making designs that crave bandwidth because gobs of that is available in workstations and servers but then they used the same designs for client too where they got hobbled by limited bandwidth. No idea if client Zen 6 gets the bandwidth it needs to unlock its full potential.

Going from 5600MT/ch to 8000MT/ch -> 43% increase in memory bandwidth.

Going from 16c to 24c -> 50% more cores ... and 15% higher IPC -> needed bandwidth increase = 58%

So .... the math doesn't seem to work out. It could be that desktop Zen 6 is indeed bandwidth limited in some applications.

It's either 26c/52t vs 52c/52t, or 24c/48t vs 48c/48t. Don't resolve the equivocation one way for AMD and the other for Intel.

For arguments sake, lets say that 1 Zen 6 core with SMT = 1.3 Intel P cores and that 1 Zen 6 core = 1.5 Intel E cores.

Intel's NVL has 16P and 32E.
16/1.3 = 12.3 Zen 6
32/1.5 = 21.3 Zen 6
NVL ~= 33.6 Zen 6 cores.

In highly threaded applications, NVL should win on the desktop.

Good point. It's like the war of attrition going on in Ukraine. AMD is in a healthy position, Intel is sickly and scrambling to hold the front lines.

AMD is in a great position to outlast Intel. Even though these threads would like to see more "maneuver warfare", Lisa is content to just grind Intel down. Time is on AMD side.

AMD has weapons to break the deadlock in server and desktop. We will see if Zen 6 notebook can deliver a breakthrough or just more of attrition warfare.

Unfortunately, this appears to be the case right now. I think AMD will pound away at the DC market with Venice (and Turin) while turning up the heat on nVidia in AI.

AMD will continue to dominate in the high end desktop with its X3D tech IMO. I am not as sure about the mobile market, but the margins there aren't that great.

That seems to be the consensus, that 18A is on par with N3P but the actual performance of the product remains to be seen.

I think 18A will sip power though. In DC the designs are usually socket power limited vs frequency limited or thermally limited.

If 18A provides good transistor density and good power characteristics, it won't matter if it only clocks to 4.5Ghz.

In the desktop .... this would be a death sentence.

 

[Cheesecake16]

For actual chiplet stuff (SED+AID+MID) I think so, but for the quasi-monolithic GPUs like ATx with just GMD+MID it's gone.

Removing the MALL in favor of a larger L2 doesn't make sense...

You can have a much larger MALL type cache then you can a L2 cache for any given die area... Reason being, the MALL doesn't have to deal with things like coherency... it can just be a pile of SRAM with no extra logic involved... so the removal of MALL makes no sense from that perspective...

Could the MALL be turned into a proper L3/L4/SLC writeback cache, sure... but outright making the L2 bigger at the expense of the MALL all together doesn't make any sense to me from an area or power perspective...

 

[511]

Intel won't drop a 52 core onto the desktop. That 52 core will go in a server, which AMD will eat for lunch.

That is a desktop part and it won't be suitable for DC due to Hybrid Architecture they are using two compute tile just like amd uses two CCX

 

[adroc_thurston]

You can have a much larger MALL type cache then you can a L2 cache for any given die area... Reason being, the MALL doesn't have to deal with things like coherency... it can just be a pile of SRAM with no extra logic involved... so the removal of MALL makes no sense from that perspective...

It makes sense when 36Gbps a pin GDDR7 is enough bandwidth to not need a 96/128M ramp in front of it.

 

[Cheesecake16]

It makes sense when 36Gbps a pin GDDR7 is enough bandwidth to not need a 96/128M ramp in front of it.

Even then it still doesn't make sense to me... the MALL in N48 is still >2.5X higher bandwidth than a 36Gbps 256b G7 memory bus... not to mention that it is lower latency which would help in RT workloads for example versus going out to memory...

 

[LightningZ71]

That's great for dGPUs. What of iGPUs? Are we expecting CUDimms or LPDDR5x or LPDDR6 to really belt out the bandwidth increases, or are iGPUs getting scaled back to less than Intel and Medusa Halo getting drug out back and filled with lead?

 

[QuickyDuck]

Going from 5600MT/ch to 8000MT/ch -> 43% increase in memory bandwidth.

Going from 16c to 24c -> 50% more cores ... and 15% higher IPC -> needed bandwidth increase = 58%

So .... the math doesn't seem to work out. It could be that desktop Zen 6 is indeed bandwidth limited in some applications.

For last couple of decades memory bandwidth is always lagging. To compensate we use cache.

 

[LightningZ71]

For last couple of decades memory bandwidth is always lagging. To compensate we use cache.

And the poster is failing to notice that the L2 cache on the CCD is highly likely to increase 50% to 48MB. Given data locality, it's likely to more than compensate for the extra cores.

 

[adroc_thurston]

not to mention that it is lower latency which would help in RT workloads for example versus going out to memory...

Too small to matter for a proper scene.

What of iGPUs?

No one uses them.

Are we expecting CUDimms or LPDDR5x or LPDDR6 to really belt out the bandwidth increases

Nope, any non-MoB LPDDR will always be slower.

or are iGPUs getting scaled back to less than Intel and Medusa Halo getting drug out back and filled with lead?

bingo!
Well, not the mdsH part. But you get the gist of it.

 

[OneEng2]

For last couple of decades memory bandwidth is always lagging. To compensate we use cache.

Yep.

And the poster is failing to notice that the L2 cache on the CCD is highly likely to increase 50% to 48MB. Given data locality, it's likely to more than compensate for the extra cores.

Yea, about that. I do agree that more cache helps ..... but not always.

Video processing in specific ... you just need to bring a lot of data into the intake and back out the exhaust. I don't think that buffering it in L2 or L3 helps.

For applications where the same data is used many times, keeping it in cache absolutely avoids main memory access and therefore the need for more main memory bandwidth.

 

[Geddagod]

I think 18A will sip power though. In DC the designs are usually socket power limited vs frequency limited or thermally limited.

If 18A provides good transistor density and good power characteristics, it won't matter if it only clocks to 4.5Ghz.

Intel has traditionally struggled much more in perf/watt at the lower end of the v/f curve vs TSMC than really any other characteristic in their nodes.

 

[Joe NYC]

That's great for dGPUs. What of iGPUs? Are we expecting CUDimms or LPDDR5x or LPDDR6 to really belt out the bandwidth increases, or are iGPUs getting scaled back to less than Intel and Medusa Halo getting drug out back and filled with lead?

Full Medusa Halo will likely be LPDDR6, still 4 memory channels, but the memory channels are 50% wider. Then bandwidth would be +50% + whatever memory speed improvement is.

From some of my superficial observations of RDNA4 is that it is less bandwidth hungry. Medusa Halo will likely be RDNA5, and may it will make more advances in the same area. So then Medusa Halo will have more performance per unit of bandwidth with bandwidth also going up.

No the downside, I have no idea how AMD expects OEMs to deal, each one on their own, with figuring out the signal integrity of faster memory speeds, greater number of traces if they already have hard time with Strix Halo.

 

[511]

AMD should do MoP for Medusa Halo like Intel is planning for NVL .
Also AMD should assume OEMs will do stupid things like they always do.

 

[igor_kavinski]

No one uses them.

That's funny coming from you because I met a Ukrainian guy who was just as poor as I used to be because we had similar old ASUS laptops and we hadn't replaced them because, you guessed it, lack of F U money. I don't think pre-war Ukrainians were well enough off to have a dGPU in every home.

 

[igor_kavinski]

AMD should do MoP for Medusa Halo like Intel is planning for NVL .

On package and off package RAM both. I really want the RAM on Medusa to be upgradable to at least 512GB.

 

[adroc_thurston]

That's funny coming from you because I met a Ukrainian guy who was just as poor as I used to be because we had similar old ASUS laptops

well I don't care about the poors.

I don't think pre-war Ukrainians were well enough off to have a dGPU in every home.

You don't need dGPU in every home.
But that's besides the point.
No one uses iGPUs. They exist to pad out TimeSpy score to look "competitive" in the market.

 

[igor_kavinski]

No one uses iGPUs. They exist to pad out TimeSpy score to look "competitive" in the market.

That's the only statement from you anyone needs to see to label you as "arrogant".

You are probably better in real life but for some reason, you like portraying your online self as a prick.

 

[Thunder 57]

well I don't care about the poors.

No one uses iGPUs. They exist to pad out TimeSpy score to look "competitive" in the market.

You didn't need to even say that about poor people everyone already knew.

Your blanket statments are annoying as hell. I may as well say "Nobody uses iGPU's, companies just like to spend plenty of valuable die space with them on every consumer CPU."

 

[igor_kavinski]

"Nobody uses iGPU's, companies just like to spend plenty of valuable die space with them on every consumer CPU."

Yes. They are doing it out of a sense of charity because otherwise the iGPU engineers and other related workers will be out of work. Also, they really must be working for potatoes because no one really cares about what they make, right?

/s

 

[poke01]

I like iGPUs cause, unlike laptops with dGPUs they offer better battery life.

The end game for laptops is MoP + LPDDR + huge dies.

Stuff the OEMs, if every vendor goes MoP they got no choice but accept the future.

 

[Doug S]

Not sure what sort of alternative reality @adroc_thurston and @LightningZ71 are living in, but in the real world the overwhelming majority of PCs are sold with iGPUs and don't ever use a dGPU. If it was true that "no one uses iGPUs" like they claim, neither AMD or Intel would bother including them, other than maybe a tiny tiny one intended only to display the BIOS screen.

 

[itsmydamnation]

You didn't need to even say that about poor people everyone already knew.

Your blanket statments are annoying as hell. I may as well say "Nobody uses iGPU's, companies just like to spend plenty of valuable die space with them on every consumer CPU."

but its pretty much true , its there because everyone else has it and you need it to sell to the very bottom of the market or even the expensive ultrabook type devices, but it is mostly rubbish to actually use .