Question Zen 6 Speculation Thread

[MS_AT]

20 GB/s difference in read speeds. Imagine latency being close to 70 ns with quad channel desktop Stix Halo instead of the current atrocious 139 ns.

My bad. I focused only on the IOD<->CCD theoretical link bandwidth, while ignoring that usually actual RAM speeds are 80% of theoretical max. Since Halo has higher theoretical max, it can squeeze the 20GB/s more to reach IOD<->CCD max.

Btw, why are you recently obsessing about latency? You know that M4 pro has much worse latency than 70ns and is quite competitive against x64 desktop parts. If you read latest C&C piece about gaming performance, you would rather wish they do something with the tiny L1i cache.

 

[Det0x]

Umm....NO.

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20 GB/s difference in read speeds. Imagine latency being close to 70 ns with quad channel desktop Stix Halo instead of the current atrocious 139 ns.

Mucho gains to be had, my friend.

Aida64 is not a good metric for anything close to "real world performance", just saying

 

[511]

Intel MLC is a better solution than AIDA64 like way better and optimized and very good functionality with different options no need to use Aida64.

Intel® Memory Latency Checker v3.11

Intel® Memory Latency Checker (Intel® MLC) is a tool used to measure memory latencies and b/w, and how they change with increasing load on the system.

www.intel.com

 

[igor_kavinski]

You know that M4 pro has much worse latency than 70ns and is quite competitive against x64 desktop parts.

Who knows what kind of tricks M4 is doing to make latency a non-issue. Don't think those tricks are coming to x86 CPUs for a few more generations (someone will get bored at Apple and jump ship for higher pay hopefully and let the x86 incumbents in on some juicy trade secrets ).

Btw, why are you recently obsessing about latency?

Because Hail_The_Brain_Slug showed how Strix Halo totally failed to show any improvement over desktop Zen 5 in Unreal compilation workload despite looking good on paper. Has to be the higher latency keeping it from performing as well as it should.

 

[poke01]

someone will get bored at Apple and jump ship for higher pay

they already did. The important ones are at Qualcomm now and other start ups. We'll see if the X Elite 2 implements something simliar to the M4 Pro cache design.

 

[igor_kavinski]

Aida64 is not a good metric for anything close to "real world performance", just saying

I checked on Phoronix. Strix Halo kicks desktop Zen 5's butt in LLM token generation speed, even when using only CPU.



It's losing in other tests to the 9900X3D either due to cache or due to higher RAM latency.

 

[poke01]

Donquidik`s 15 sec 65 ms score: PYPrime - 2b with BenchMate with aDDR5 SDRAM

The DDR5 SDRAM @ 998.2MHzscores getScoreFormatted in the PYPrime - 2b with BenchMate benchmark. Donquidikranks #1586 worldwide and #863 in the hardware class. Find out more at HWBOT.

esports.hwbot.org

Strix Halo LPDDR5X 8000MHz :


Compare that with 256-bit DDR5 6400MHz from @Hail The Brain Slug result:


DDR5 is better but for laptops that need unified memory LPDDR5 is the way to go but there are drawbacks.

 

[StefanR5R]

AMD is trying to increase mobile market share but is failing.

To gain mobile market share basically means to cater to OEM's habits and preferences.
What are these? I don't know, but I guess:
– New laptop design must be same as old laptop design with only minimal low-risk udates.
– Or, new laptop design must have been developed and debugged mostly by the CPU maker and gifted to the OEM.
– Or if the CPU maker didn't actually do it himself, he did at least fund most of it.
– Cheap BOM.
– A certain refresh cycle periodicity. (Refresh just needs to look like new, doesn't actually have to be new materially.)
– Miscellaneous sticker compatibility.

 

[eek2121]

We don't have any indication that Zen 6 will be anything more than 15% ST and maybe 40% MT. Meanwhile, Intel is bringing core spam to the party with Nova Lake. Even if Intel messes up the ST performance, they still end up being competitive in the MT department with real threads instead of virtual ones. That's not what the market wants. What the market really wants is

1) Intel being forced to bring out an expensive to manufacture CPU that beats Zen 6 decisively, at least in MT and approaching HEDT performance of Threadripper.

2) Intel being forced to sell their lower performing CPUs at a hefty discount compared to Zen 6.

No.1 compels AMD to strike back with more power in whatever way they deem necessary.

No.2 forces AMD to respond in kind and get into a serious price war.

We, the consumers, watch with glee and eat popcorn and enjoy better, cheaper CPUs.

The upcoming face-off between Zen 6 and Nova Lake seems to be more of the same. Boring status quo. Nothing exciting.

Competition needs to heat up.

Intel dropped hyperthreading, though, so they aren’t going to beat Zen6 by much, if at all.

It's true that Intel margin is going down and AMD margin is going up. But as of last quarter:
Intel client operating margin: 26%
AMD client operating margin: 21%

That was due to write offs due to political nonsense. Excluding the write offs, it would have been > 50%.

Next few quarters will be abnormally high for the same reason. All that hardware/IP they wrote off? It turns out they now get to sell it at near 100% margins.

 

[MS_AT]

I checked on Phoronix. Strix Halo kicks desktop Zen 5's butt in LLM token generation speed, even when using only CPU.

If you only verified the speed of desktop RAM in this comparison and then computed the ratio of observed performance, to the ratio of memory speed of two platforms your post would be more valuable. Right now, it does not allow one to make any conclusions, since 8000MT/s is not the default speed people use. Just saying

Because Hail_The_Brain_Slug showed how Strix Halo totally failed to show any improvement over desktop Zen 5 in Unreal compilation workload despite looking good on paper. Has to be the higher latency keeping it from performing as well as it should.

Halo shouldn't show any improvement in compilation workloads against Zen5 to begin with, code compilation is not memory bandwidth bound and that is the only advantage Halo brings to the table while it's at disadvantage from clock and latency point of view. The problem there, was getting Windows to behave and when it started to use full chip the power draw was not competitive any more with tuned desktop chip. Why? We don't know. Maybe it was memory latency. Maybe something else. The fact is it wasn't faster than 88W locked 9950x3d.

 

[Hail The Brain Slug]

If you only verified the speed of desktop RAM in this comparison and then computed the ratio of observed performance, to the ratio of memory speed of two platforms your post would be more valuable. Right now, it does not allow one to make any conclusions, since 8000MT/s is not the default speed people use. Just saying


Halo shouldn't show any improvement in compilation workloads against Zen5 to begin with, code compilation is not memory bandwidth bound and that is the only advantage Halo brings to the table while it's at disadvantage from clock and latency point of view. The problem there, was getting Windows to behave and when it started to use full chip the power draw was not competitive any more with tuned desktop chip. Why? We don't know. Maybe it was memory latency. Maybe something else. The fact is it wasn't faster than 88W locked 9950x3d.

The unreal compilation workload shows similar memory activity in HWINFO to running a memory stress test like karhu or occt memory stress.

I think compilation might be more memory intensive in some cases than you might think.

Curious, though, why strix halo would run at higher frequency compared to the 9950X3D at 88W while not performing faster. Is it also memory latency sensitive?

Latency seems like an obvious culprit, but my new setup with 256GB on a 9950X3D is within margin of error while having significantly worse latency than my original 96GB 9950X3D setup I tested against strix halo.

Edit:
9950X3D + 256GB 6400C32 : 1757.34 seconds
9950X3D + 96GB 6000C30 tuned timings: 1742.13s

 

[Win2012R2]

What are these? I don't know, but I guess

- co-marketing dollars from Intel

This time however things might actually be different - if AMD offers them better margins

 

[Win2012R2]

If they achieve 80%+ marketshare in datacenter, then I think you’ll see an AMD that’s focused on more areas

Intel will go bust at that point so the rest will fall into AMDs lap.

It's so over.

 

[StefanR5R]

Curious, though, why strix halo would run at higher frequency compared to the 9950X3D at 88W while not performing faster. Is it also memory latency sensitive?

At a given power limit, the waiting for memory accesses — IOW, the managing of bubbles in the processor pipeline — can be performed at a higher clock speed than actual compilation — IOW, than having actually busy stages in the pipeline. [ <- copy+paste ;-) ]

Edit,

I think compilation might be more memory intensive in some cases than you might think. [...] Is it also memory latency sensitive?

for comparison, chipsandcheese's "Linux Kernel Compile, tinyconfig" test is a comparably low-IPC workload which is significantly CPU frontend latency bound and memory latency bound. (E.g.: "AMD’s Ryzen 9950X: Zen 5 on Desktop")

 

[igor_kavinski]

Latency seems like an obvious culprit, but my new setup with 256GB on a 9950X3D is within margin of error while having significantly worse latency than my original 96GB 9950X3D setup I tested against strix halo.

Edit:
9950X3D + 256GB 6400C32 : 1757.34 seconds
9950X3D + 96GB 6000C30 tuned timings: 1742.13s

They have about the same first word latency.

 

[Joe NYC]

Umm....NO.

View attachment 128978
View attachment 128979

20 GB/s difference in read speeds. Imagine latency being close to 70 ns with quad channel desktop Stix Halo instead of the current atrocious 139 ns.

Mucho gains to be had, my friend.

Strix Halo would benefit from V-Cache even more that desktop, considering its memory latency.

 

[Joe NYC]

That was due to write offs due to political nonsense.

The write-offs were in the datacenter category. I listed client category.

Excluding the write offs, it would have been > 50%.

You may be thinking gross margin, which is higher than operating margin.

I used operating margins of both Intel and AMD to get (close to) apples to apples comparison.

Next few quarters will be abnormally high for the same reason. All that hardware/IP they wrote off? It turns out they now get to sell it at near 100% margins.

Hopefully, they can convert what was written off to sales, but that improve datacenter division and company overall. Client division will have its own trajectory.

 

[Joe NYC]

To gain mobile market share basically means to cater to OEM's habits and preferences.
What are these? I don't know, but I guess:
– New laptop design must be same as old laptop design with only minimal low-risk udates.
– Or, new laptop design must have been developed and debugged mostly by the CPU maker and gifted to the OEM.
– Or if the CPU maker didn't actually do it himself, he did at least fund most of it.
– Cheap BOM.
– A certain refresh cycle periodicity. (Refresh just needs to look like new, doesn't actually have to be new materially.)
– Miscellaneous sticker compatibility.

It seems that AMD may already be doing most of those things. One thing that Intel is probably doing which AMD is not, is give OEMs money for advertising.

 

[adroc_thurston]

One thing that Intel is probably doing which AMD is not, is give OEMs money for advertising.

AMD does do that.

 

[Doug S]

They are going for profit over market penetration. It's like they don't think they can continue to make great products so may as well make as much money as possible. Prime example is not changing the IOD for Zen 5 for DDR5-8000 1:1 RAM speeds. Also, no Strix Halo with quad channel DDR5-8000 for desktop. They can certainly do a lot better but they are more occupied with making money and playing it safe rather than making a serious effort to drive Intel out of the market with products that Intel has no hope of beating.

AMD doesn't want to drive Intel out of the market anymore than Intel wanted to drive AMD out. If Intel had wanted to, they could have bankrupted AMD on several occasions. They held back and left just enough scraps for AMD to survive, because they knew if AMD went under and they held a complete and total x86 monopoly they'd be subject to greater antitrust scrutiny not only in the US but the EU and elsewhere in the world.

The only times Intel took its boot off AMD's face was when they followed the 10 GHz pied piper down the P4 path, and more recently when AMD recovered from their Bulldozer malaise - which happen around the same time Intel got stuck on 10nm for half a decade, and had been coasting on their CPU core designs for so long they forgot how to do anything other than coast.

 

[igor_kavinski]

They held back and left just enough scraps for AMD to survive, because they knew if AMD went under and they held a complete and total x86 monopoly they'd be subject to greater antitrust scrutiny not only in the US but the EU and elsewhere in the world.

Not sure about that. M$ is a monopoly. So is Apple. What's Intel so afraid of?

 

[OneEng2]

I'm guessing they will use N2 for their ARM APU and mobile Zen 6 which will use up any quota they had for desktop chips.

I think you are correct in the sense that the N2 quota, and the process cost (and thus AMD's margins) will determine which products end up produced on N2.

They will use it for the most profitable things -
1. MI400 chiplets
2. Zen6 server chiplets
3. Leftovers here

N3E should work nicely in mobile, which requires high volume anyway that N2 unlikely to provide, certainly not at margins needed to pay for new wafers.

I think you are likely very close to correct. This would make very good sense for AMD IMO.

Looking at the escalating chip prices by TSMC, I am not convinced that anything other than zen6c will be 2nm on AMD side

I agree that 2nm will likely be used only for high margin products ..... just like N3E is used today for Zen 5c server. It is possible as you speculate that ONLY Venice Dense will use 2nm .... but we will see.

Nope. They will use N2 for desktop, server and laptop replacement. Mainstream mobile is N3 class.

It doesn't make much sense to me for this to be the case. We will see.

We don't have any indication that Zen 6 will be anything more than 15% ST and maybe 40% MT

If it's 15% ST and then increased the core count by 50%, wouldn't MT be more like 57%?

AMD is trying to increase mobile market share but is failing.

AMD is making money hand over fist. I wouldn't say they are failing. Furthermore, they may be losing mobile market share, but they are punishing Intel terribly financially. The current trend and Intel strategy is not sustainable. Looks to me like AMD has a better chess game going on.

$600+ motherboards for this would be a non-starter

Completely agree.

At least, AMD will not be at a node disadvantage, since the mobile parts will be combination of N3P and N2P, while Intel will only be on par with N3P.

I am guessing you say this because you believe that N3P is about equal to 18A? While this COULD be true, I don't think there is any evidence to suggest it. Personally, I expect 18A to be close to N2 .... but cost more and possibly clock slower to some extent. In DC, the lower clock shouldn't make any difference .... so it might be a more potent technology than many are thinking .... at least for DC.

They’re rapidly gaining marketshare in datacenter. It’s every business person’s dream to be able to rapidly gain marketshare in the highest profit venue. They’d have to be insane to devote too many resources to client when there is still ground left in datacenter.

LOL. I agree. AMD's "Server First" design philosophy has been a very big success financially. I think they will get around to pushing their advantage in other markets, but as you say, they will stay focused on DC and AI for Zen 6 and Zen 7 IMO.

They're literally maintaining their share by shedding operating margin.

Yep. As I stated earlier, this is a pretty bad chess strategy for Intel.

Except, client (for CPU) is twice the size of datacenter.

By unit sales, client is 20-30x the size of datacenter.

By revenue, they are about equal (~20-30bn/yr)

By profit .... not even close DC is MUCH more profitable than client.

DC is, by far, the most desirable market to be gaining share in. It isn't even close.

Intel dropped hyperthreading, though, so they aren’t going to beat Zen6 by much, if at all.

Oh, I rather think a 52 core NVL will handily best a Zen 6 24c/48t cpu in highly MT applications. I am guessing by 30%.

 

[Markfw]

I think you are correct in the sense that the N2 quota, and the process cost (and thus AMD's margins) will determine which products end up produced on N2.

I think you are likely very close to correct. This would make very good sense for AMD IMO.

I agree that 2nm will likely be used only for high margin products ..... just like N3E is used today for Zen 5c server. It is possible as you speculate that ONLY Venice Dense will use 2nm .... but we will see.

It doesn't make much sense to me for this to be the case. We will see.

If it's 15% ST and then increased the core count by 50%, wouldn't MT be more like 57%?

AMD is making money hand over fist. I wouldn't say they are failing. Furthermore, they may be losing mobile market share, but they are punishing Intel terribly financially. The current trend and Intel strategy is not sustainable. Looks to me like AMD has a better chess game going on.

Completely agree.

I am guessing you say this because you believe that N3P is about equal to 18A? While this COULD be true, I don't think there is any evidence to suggest it. Personally, I expect 18A to be close to N2 .... but cost more and possibly clock slower to some extent. In DC, the lower clock shouldn't make any difference .... so it might be a more potent technology than many are thinking .... at least for DC.

LOL. I agree. AMD's "Server First" design philosophy has been a very big success financially. I think they will get around to pushing their advantage in other markets, but as you say, they will stay focused on DC and AI for Zen 6 and Zen 7 IMO.

Yep. As I stated earlier, this is a pretty bad chess strategy for Intel.

By unit sales, client is 20-30x the size of datacenter.

By revenue, they are about equal (~20-30bn/yr)

By profit .... not even close DC is MUCH more profitable than client.

DC is, by far, the most desirable market to be gaining share in. It isn't even close.

Oh, I rather think a 52 core NVL will handily best a Zen 6 24c/48t cpu in highly MT applications. I am guessing by 30%.

Intel won't drop a 52 core onto the desktop. That 52 core will go in a server, which AMD will eat for lunch.

 

[StefanR5R]

I rather think a 52 core NVL will handily best a Zen 6 24c/48t cpu in highly MT applications. I am guessing by 30%.

The rumored Intel chip which is colloquially called a "52 cores" chip is, throughput-wise, a 48 threads chip with dual-channel memory and ??? Watts power budget.

Now, power. If Intel's and AMD's offerings had the same power efficiency, Intel's would need 130% power budget in order to feature 130% throughput...

 

[Thunder 57]

Intel won't drop a 52 core onto the desktop. That 52 core will go in a server, which AMD will eat for lunch.

Yes, this reminds me of the Zen 2 Adored TV "leak" that promnised high core counts at bargain prices. It was never going to happen.If it makes it to DT it will cost a lot.