Question Zen 6 Speculation Thread

[511]

Just scrap it and than move to RRF

This has been a persistent problem with every Xeon since ICL-SP and it's not changing (for now, anyway).

well it's not the IFS that is screwing around it's an Intel as a whole problem

 

[adroc_thurston]

than move to RRF

Literally dead.
No one wanted Atom Xeons pmuch.

 

[511]

Literally dead.

Not Dead yet

 

[adroc_thurston]

Not Dead yet

It is.

 

[madtronik]

Literally dead.
No one wanted Atom Xeons pmuch.

No reason when the dense cores from AMD are so much better. Without AMD it could have garnered sales. though.

 

[OneEng2]

Lets say that Turin D with 256 cores is worth 1.4 Intel E cores in MT including the effect of AVX512.

256 cores of Zen 6c = 1.4x256=358 CWF cores.

Seems like it would be a blood bath in favor of Turin D.

 

[511]

Lets say that Turin D with 256 cores is worth 1.4 Intel E cores in MT including the effect of AVX512.

256 cores of Zen 6c = 1.4x256=358 CWF cores.

Turin D is 192C btw that is Venice Dense

 

[OneEng2]

Turin D is 192C btw that is Venice Dense

Not sure why I keep making that mistake.

Of course I meant to say "Venice" for Zen 6. Damn old age .

 

[OneEng2]

CWF could indeed be good competition for VENICE D though...

192*1.4 = 269 Intel E Cores. CWF = 288 E Cores.

 

[DrMrLordX]

CWF could indeed be good competition for VENICE D though...

Nah probably not. It's clearly targeted at Turin-dense and it's still not clear what the perf/watt situation will look like for Clearwater Forest. At this point I'd say it's going to be another situation like Sierra Forest where Intel comes out with something that probably has better perf/watt than the outgoing AMD chip (in this case, Turin-dense) but now tack another ~6-12 months onto the delay of the Intel product. At least Sierra Forest managed to release near the end of Bergamo's market window. Clearwater Forest looks like it'll be squaring off against Venice-dense where Intel has no chance.

 

[511]

Clearwater Forest looks like it'll be squaring off against Venice-dense where Intel has no chance.

It is Q1 26 product it will only have like 3-6 months vs Turin Dense before Venice Dense launches.

 

[Josh128]

CWF could indeed be good competition for VENICE D though...

192*1.4 = 269 Intel E Cores. CWF = 288 E Cores.

How so? Venice Dense is going to be 256 hyperthreaded cores per socket. 256*1.4= 358 or just by threads, 512 AMD vs 288 Intel, per socket.

 

[techjunkie123]

How so? Venice Dense is going to be 256 hyperthreaded cores per socket. 256*1.4= 358 or just by threads, 512 AMD vs 288 Intel, per socket.

It's a typo he meant TURIN D. I presume.

 

[OneEng2]

How so? Venice Dense is going to be 256 hyperthreaded cores per socket. 256*1.4= 358 or just by threads, 512 AMD vs 288 Intel, per socket.

It's a typo he meant TURIN D. I presume.

Yes. I am positively getting mind blanked between Turin and Venice for some stupid reason!

Venice D should do a comfortable tap dance on CWF.... but CWF should eclipse Turin D in many applications. I am not quite sure about AVX512 enabled apps though because I am not certain how effective (if at all) CWF will be at executing AVX.

 

[Abwx]

Lets say that Turin D with 256 cores is worth 1.4 Intel E cores in MT including the effect of AVX512.

Just SMT account roughly for 1.4x the perf of Zen 5 ST perf, and in your compaison IPC difference is not accounted, so i let you imagine if AVX512 is added in the mix

FTR 7Zip, wich doesnt use AVX, has a 1.44x SMT scaling on Zen 5, beside it s a load that is quite representative of servers perfs.

 

[adroc_thurston]

beside it s a load that is quite representative of servers perfs.

Not really, but yes. SMT is very important.

 

[OneEng2]

Not really, but yes. SMT is very important.

... and is surprisingly effective for performance per transistor area it uses.

Still, Intel's P and E core strategy looked pretty promising at first. I think it still looks pretty good for desktop and laptop .... but in the lucrative DC? I think the use of identical architectures for P and E cores is a more effective strategy.

It seems like DC workloads better utilize SMT (and AVX512). It isn't that SMT doesn't help in Desktop and laptop, just not as much as DC.

But then, AMD has a really great solution for desktop and laptop with 3D vCache to improve single threaded performance.

 

[basix]

In some cases, SMT can reach close to 2x performance gains. This can happen in I/O bound situations, e.g. harddisk or networking limitations.
And in case of todays many cloud services, more threads can help as well. There you often do not need maximum performance per thread, but more cores and threads and maximum energy efficieny.

 

[Geddagod]

... and is surprisingly effective for performance per transistor area it uses.

Still, Intel's P and E core strategy looked pretty promising at first. I think it still looks pretty good for desktop and laptop .... but in the lucrative DC? I think the use of identical architectures for P and E cores is a more effective strategy.

It seems like DC workloads better utilize SMT (and AVX512). It isn't that SMT doesn't help in Desktop and laptop, just not as much as DC.

But then, AMD has a really great solution for desktop and laptop with 3D vCache to improve single threaded performance.

I think Intel's strategy was outright better, but it was too costly to host two separate teams like that when your company is struggling they way they were.
One can still have 2 separate architectures but have them both be able to support AVX-512. Rumored to be the case in NVL.
I could imagine a world where the E-cores added SMT, and became the "main" server sku, while the P-core skus removed SMT, and increased cache per core and AVX-512 and AMX capabilities for HPC, or even hyper scalers who wanted some skus with very high per-core perf and cache/memory bandwidth per core.

 

[511]

They answer was Unified Core for this end of 2028 at best though.

 

[OneEng2]

I think Intel's strategy was outright better, but it was too costly to host two separate teams like that when your company is struggling they way they were.
One can still have 2 separate architectures but have them both be able to support AVX-512. Rumored to be the case in NVL.
I could imagine a world where the E-cores added SMT, and became the "main" server sku, while the P-core skus removed SMT, and increased cache per core and AVX-512 and AMX capabilities for HPC, or even hyper scalers who wanted some skus with very high per-core perf and cache/memory bandwidth per core.

I'm not so sure. There are lots of issues with having dissimilar architectures between P and E cores. Certainly the validation and development costs are one of the many issues.

They answer was Unified Core for this end of 2028 at best though.

The fact that Intel's roadmap is to have a unified core strategy in the future is a VERY strong indicator that Intel engineering also believes that dissimilar architectures for P and E cores has too many down sides.

 

[adroc_thurston]

They answer was Unified Core for this end of 2028 at best though.

2029

 

[511]

2029

I said at best that's mid

 

[adroc_thurston]

I said at best that's mid

No, it's 2029 at best.

 

[Markfw]

I'm not so sure. There are lots of issues with having dissimilar architectures between P and E cores. Certainly the validation and development costs are one of the many issues.

The fact that Intel's roadmap is to have a unified core strategy in the future is a VERY strong indicator that Intel engineering also believes that dissimilar architectures for P and E cores has too many down sides.

This is a Zen 6 thread, NOT an Intel one.