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Question Zen 6 Speculation Thread

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soresu said:
Perhaps if the 6c parts are 'double pumping' AVX512 execution, but in general the dense parts are designed for that feature to the exclusion of other gains
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Yet, they are supposed to replace non dense parts in 'mainstream' segment so they cannot have worse ST performance than the old ones. The same or higher, what suggest they should be able to match the clock of current gen parts. Not that they will close the freq gap to non dense part of their own generation.

Also I doubt all core frequency is quoted under heavy AVX512 load😉

But we will see in a year😉
 
MS_AT said:
Yet, they are supposed to replace non dense parts in 'mainstream' segment so they cannot have worse ST performance than the old ones. The same or higher, what suggest they should be able to match the clock of current gen parts. Not that they will close the freq gap to non dense part of their own generation.

Also I doubt all core frequency is quoted under heavy AVX512 load😉

But we will see in a year😉
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Consumer dense parts are not going to be packed at 32 cores a piece tho (much as I would give a kidney to have them so 😂).

I was talking about EPYC as the 32 core CCDs were the topic, and they will definitely not be pushing hard for clock increases with such a meaty core count increase.
 
soresu said:
Consumer dense parts are not going to be packed at 32 cores a piece tho (much as I would give a kidney to have them so 😂).

I was talking about EPYC as the 32 core CCDs were the topic, and they will definitely not be pushing hard for clock increases with such a meaty core count increase.
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So was I, by mainstream I meant non dense Turin parts😉
 
Given the timelines TSMC has given for both cutting edge logic nodes and the SOIC roadmap, I highly, highly, doubt they'd use N4 for anything related to the cache die by 2027/2028. They'll probably go A16 CCD + N2 SRAM die. 1747258467521.png1747258478341.png
 
Darkmont said:
Given the timelines TSMC has given for both cutting edge logic nodes and the SOIC roadmap, I highly, highly, doubt they'd use N4 for anything related to the cache die by 2027/2028. They'll probably go A16 CCD + N2 SRAM die. View attachment 123777View attachment 123778
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After N4, the SRAM scaling is far worse than cost scaling, so no point in going into negative price-performance.

And by the time of the release of Zen 7, N4 will be a very economical trailing node with endless capacity. Same as N6 is now.
 
SolidQ said:
Some leaks about Zen7
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This looks to me like one implementation - of server a chiplet. We can take some clues as to what a client chiplets will look like, but not necessarily the same as server.

So looks like AMD is going up to 2 MB L2 on the main core die (which should have some IPC implications).
And then, they are going from 4 MB per core to 7 MB per core (presumably, if there is 1:1 ratio of cores to cache slices).

So for server variants, these are improvements from current base implementations. If that parallels client (with lower core count, maybe 16), it will also be improvement fro 4MB L3 per core.

But V-Cache currently offers 12 MB L3 per core, so we will see if there is going to be a way to maintain or even increase L3 per core using a different method (or stacking ore cache dies).
 
reaperrr3 said:
At the very least, the 32c CCD for Venice-D probably needed the density and efficiency gains of N2 anyway.
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"Needed" is the key word and tricky phrase here. 32c is a possible engineering feat; however, it is a VERY expensive engineering feat that I believe AMD will avoid. I would be more likely to guess that AMD will have an 8 IOD design to double the CCD count of 16c CCDs.
Joe NYC said:
As of this current quarter, Year over Year AMD ASPs are up 43%, double digits in QoQ. While Intel is forced to cut prices due to lack of interest from Premium segment buyers. That's where AMD wants to be.
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Yes, this is true. It is ALSO true that AMD is doing this from a full die shrink behind Intel.
511 said:
My take Zen 6 is Vanilla N2 if it is N2P it is launching H2 27.
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Agree.
 
Joe NYC said:
After N4, the SRAM scaling is far worse than cost scaling, so no point in going into negative price-performance.
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Totally agree. Why pay double for 15%?

As for the speculation on Zen 7, I'll give it my same general speculation as Zen 6.

In general, AMD is going to embrace the modular design and more chiplets. They are perfecting their multi-chip designs making their compute less and less memory latency dependent while simultaneously lowering latency with advanced packaging techniques.

I feel the people who believe AMD will move back to monolithic designs are way off base .... but that is just my opinion.

I also believe that AMD is going to be primarily targeting DC with their architectures. Desktop and Laptop are going to get hand-me-down technology with the one exception of ever more potent 3D cache designs.

I think that we will continue to see pretty decent improvement to gaming performance from generation to generation of X3D chips. I think that ST performance will be fairly lack luster with the exception of new instructions moving forward. MT will be where most of the big improvements are.

AI accelerators are going to evolve as AI optimizations in training and fetching techniques continue to evolve. Despite what many people believe, local AI processing is going to be the next big thing. All that "wasted" silicon space will get used exponentially more moving forward in the next few years.

I am still not bought into the 32c Zen 6c part.... but then I would love to be proven wrong 😉.
 
OneEng2 said:
Totally agree. Why pay double for 15%?

As for the speculation on Zen 7, I'll give it my same general speculation as Zen 6.

In general, AMD is going to embrace the modular design and more chiplets. They are perfecting their multi-chip designs making their compute less and less memory latency dependent while simultaneously lowering latency with advanced packaging techniques.

I feel the people who believe AMD will move back to monolithic designs are way off base .... but that is just my opinion.

I also believe that AMD is going to be primarily targeting DC with their architectures. Desktop and Laptop are going to get hand-me-down technology with the one exception of ever more potent 3D cache designs.

I think that we will continue to see pretty decent improvement to gaming performance from generation to generation of X3D chips. I think that ST performance will be fairly lack luster with the exception of new instructions moving forward. MT will be where most of the big improvements are.

AI accelerators are going to evolve as AI optimizations in training and fetching techniques continue to evolve. Despite what many people believe, local AI processing is going to be the next big thing. All that "wasted" silicon space will get used exponentially more moving forward in the next few years.

I am still not bought into the 32c Zen 6c part.... but then I would love to be proven wrong 😉.
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I wonder if the chips shown in MLID video has 33 dense cores of 33 full cores.

33 full cores would be feasible with similar die size as 32 core (dense) Zen 6 chiplet after shrink an L3 removal.

But more likely, it is a 33 dense cores, with much smaller core die size than Zen 6. Unless there is some new transistor bloat added, the A14 die with cores could be 40-50% smaller than Zen 6. Very cost competitive.

I think the full core die will be a different story, but may have a similarities. Perhaps the full core die will have 16 cores on A14 + 12 MB L3 per core (same as V-Cache chip) on LE die, making this the default full core CCD, shared with premium desktop and notebook segments. This die should be in the same ballpark as 12 core Zen 6 on N2 with L3 on-board.
 
Joe NYC said:
This looks to me like one implementation - of server a chiplet. We can take some clues as to what a client chiplets will look like, but not necessarily the same as server.

So looks like AMD is going up to 2 MB L2 on the main core die (which should have some IPC implications).
And then, they are going from 4 MB per core to 7 MB per core (presumably, if there is 1:1 ratio of cores to cache slices).

So for server variants, these are improvements from current base implementations. If that parallels client (with lower core count, maybe 16), it will also be improvement fro 4MB L3 per core.

But V-Cache currently offers 12 MB L3 per core, so we will see if there is going to be a way to maintain or even increase L3 per core using a different method (or stacking ore cache dies).
Click to expand...
clickbait ...
 
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