We are talking about Zen 6 LP cores. So one AMX unit per 2C/4C cluster sounds very reasonable to me. I assume the big ones will have dedicated AMX units per core (or at least more AMX units per cluster than just 1). Kepler_L2 just said one unit per 2 cores. OK for me.
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adroc_thurston
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I wonder if people were saying the same thing about FPUs in the 80s
They means AMD so we will get only APUs or they means nVidia which will admit that spending time on gamers is a waste of time?
adroc_thurston
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Means the discrete presence is whatever dies from other markets they have on hand.They means AMD so we will get only APUs or they means nVidia which will admit that spending time on gamers is a waste of time?
RDNA5 has 4 parts, but 6 can have 1. Or 3. And none are built to intercept any Nvidia configs.
How can you say that? Do you have any info on DMR for example? Anything to back up your "underestimation of the decade" claim? Because as an AMD shareholder I would appreciate that outcome a lot.
For AMD it makes sense to build GPUs like AT3 and AT4. Dual-Use for Mobile and Desktop (and small form factor ML/AI machines due to large memory pool support). And due to dual-use, AMD gets much better economies of scale compared to historic dGPUs. The large memory pool additionally opens up other market opportunities, where memory capacity is more important than peak FLOPS or memory bandwidth (professional-use dGPUs for scientific simulations, EDA, ML/AI and maybe also rendering).
AT2 and AT0 seem to be leveraging dual-use as well (Microsoft's XBox Next and game streaming). Makes sense as well at only 10-20% dGPU market share and de-risks your chip design project.
So from a HW- and chip-design perspective, AMD seems to act very reasonable for RDNA5.
Looking at RDNA6, AMD could double-down on that philosophy by finally designing a fully chiplet based architecture. One GPU chiplet for all market needs. Scale-up according to market conditions (1...N chiplets). With that you do not directly compete with Nvidia GPU SKUs. But you could scale your GPUs accordingly if necessary. And you get very nice economies of scale.
One important thing is nearly completely independent from HW design: FSR and ROCm support. Besides of designing good HW, AMD needs to put enough effort into its gaming GPU related SW portfolio. Otherwise AMD has good consumer/prosumer HW but due to lacking SW it underperforms.
AT2 and AT0 seem to be leveraging dual-use as well (Microsoft's XBox Next and game streaming). Makes sense as well at only 10-20% dGPU market share and de-risks your chip design project.
So from a HW- and chip-design perspective, AMD seems to act very reasonable for RDNA5.
Looking at RDNA6, AMD could double-down on that philosophy by finally designing a fully chiplet based architecture. One GPU chiplet for all market needs. Scale-up according to market conditions (1...N chiplets). With that you do not directly compete with Nvidia GPU SKUs. But you could scale your GPUs accordingly if necessary. And you get very nice economies of scale.
One important thing is nearly completely independent from HW design: FSR and ROCm support. Besides of designing good HW, AMD needs to put enough effort into its gaming GPU related SW portfolio. Otherwise AMD has good consumer/prosumer HW but due to lacking SW it underperforms.
adroc_thurston
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Anyone who knows 2026/2027 server comp positioning would tell you that.
yes it sucks a fat one.
well, pay me, and I'll tell you.
uh, no, GPU tiling is a win-more scenario.
It's not cost-effective to build GPUs with tiling since SoIC-X d2w costs + AID per config make it unviable.
they need the shills. and the choppa. they have neither; thus they're dead.
Not sure if SoIC is required. Regular 2.5D could also be an option which could be more cost effective.
So no AID + stacked Die, only one GPU chiplet for 2.5D integration.
adroc_thurston
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It is.
a) how would that work
b) where the pJ/b be at
How would that work?
Look at Nvidias B200 and Rubin chips. Do you see any 3D-Stacking there? I do not. Same as M3 Max. Just two chips side by side. The chips contain all you need (SMs, command processor, LLC, memory interface). Glue multiple of them together with 2.5D packaging. But instead of using only 2 Die, use N Die.
This is not much different compared to AT3 and AT4 packaging with a host Die. Just that you now could chain multiple GPU chiplets to build a bigger GPU. Maybe 1...4x GPU Die (e.g. 32/64/96/128 CU in total)
This is not much different compared to AT3 and AT4 packaging with a host Die. Just that you now could chain multiple GPU chiplets to build a bigger GPU. Maybe 1...4x GPU Die (e.g. 32/64/96/128 CU in total)
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marees
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adroc_thurston
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Extremely extensive SoIC-X tour de force.
Tiled gfx is always a win-more solution.
adroc_thurston
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compute.
a stinky mess (and TBDR, not comparable at all).
Doesn't work for modern IMR GPUs doing modern engines.
Split LLCs in particular would be catastrophic.
There is no 'host die' the GPU is self-sufficient.
CCD attach just gives you an APU config.
N4C would have already featured split LLCs, my friend. Multiple AID connected with silicon bridges.
The difference between my idea and N4C would simply be, that you do not have separated SED and AID. These two would be merged into one Die and therefore 3D-Stacking is not required. The base concept regarding splitting the GPU in multiple parts is the very same. If N4C would have worked, my idea would work as well.
The difference between my idea and N4C would simply be, that you do not have separated SED and AID. These two would be merged into one Die and therefore 3D-Stacking is not required. The base concept regarding splitting the GPU in multiple parts is the very same. If N4C would have worked, my idea would work as well.
adroc_thurston
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No, MALL was striped (by the nature of being a memside cache).
It's not, N4c tile to tile was SoIC everywhere. No 2.5D present.
What about this picture? Can you see the CoWoS-L silicon bridges?
www.techpowerup.com
AMD "Navi 4C" GPU Detailed: Shader Engines are their own Chiplets
"Navi 4C" is a future high-end GPU from AMD that will likely not see the light of day, as the company is pivoting away from the high-end GPU segment with its next RDNA4 generation. For AMD to continue investing in the development of this GPU, the gaming graphics card segment should have posted...
adroc_thurston
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well, not oS, there's no 2.5D slab.Can you see the CoWoS-L silicon bridges?
It's bridges hybrid bonded to the AIDs on top.
You know, pkg diagrams are trivial to read.
That would be a very weird packaging procedure:
No hybrid bonding of one overlapping chip to two other chips has ever been shown (not to my knowledge).
EMIB / EFB alike packaging would make much more sense to me. Especially for N4C if considering it would have featured MALL. RDNA3 even could afford to split its MALL up into 6 slices with organic 2.5D packaging. Using silicon bridges would be technologically more advanced than that.
A split L2-Cache would be more demanding, I agree on that one. But I see hope there. AMD does revamp its L0/L1 caching with RDNA5. That should lead to reduced bandwidth requirements towards L2$. And the local SE / WGP scheduling paradigm should lead to the fact that each shader engine works on its own as much as possible, mostly working with the locally attached L2$ slice. Data locality paradigms should minimize global L2$ accesses across multiple Die anyways. Yes, L2$ splitting is more difficult. But such problems can be solved by smart ideas and good engineering
No hybrid bonding of one overlapping chip to two other chips has ever been shown (not to my knowledge).
EMIB / EFB alike packaging would make much more sense to me. Especially for N4C if considering it would have featured MALL. RDNA3 even could afford to split its MALL up into 6 slices with organic 2.5D packaging. Using silicon bridges would be technologically more advanced than that.
A split L2-Cache would be more demanding, I agree on that one. But I see hope there. AMD does revamp its L0/L1 caching with RDNA5. That should lead to reduced bandwidth requirements towards L2$. And the local SE / WGP scheduling paradigm should lead to the fact that each shader engine works on its own as much as possible, mostly working with the locally attached L2$ slice. Data locality paradigms should minimize global L2$ accesses across multiple Die anyways. Yes, L2$ splitting is more difficult. But such problems can be solved by smart ideas and good engineering
adroc_thurston
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That's the whole point.
N4c was a novel packaging exercise + system design innovation.
Again, MALL is striped across the address space.
Not "demanding", unworkable for client.
Higher than ever.
adroc_thurston
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As is everything Nvidia since Maxwell.
You're still have no real tile storage (or a real tiler) to distribute screenspace across.
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