Question Zen 6 Speculation Thread

[poke01]

AMD makes up their lack of leading ST for leading nT. For AMD industry leading nT makes more sense.


Since Intel sells a lot of client computers, it not having leading ST is kinda of a bummer.

 

[511]

For clients Cheap stuff is the one that sells not the leading one arl/lnl are clearly better but RPL outsells them.

 

[Meteor Late]

The outlook is that the performance gap with the Apple M-series CPUs keeps widening, right? Those are also due another node jump, and the compounded annualized performance growth rate over say 2023-2027 doesn’t seem to be even close to Apple’s - or am I underestimating the clock • ipc improvements?

I don't think it is widening, AMD will probably get around 25% 1t uplift with Zen 6 with the double node jump, though in Laptops it's a single node jump I think. I expect Apple to match that 25% uplift between M4 and M6.

 

[adroc_thurston]

though in Laptops it's a single node jump I think

Mainstream yes, anything with margins is N2p though.

 

[511]

I don't think it is widening, AMD will probably get around 25% 1t uplift with Zen 6 with the double node jump, though in Laptops it's a single node jump I think. I expect Apple to match that 25% uplift between M4 and M6.

In mobile doubt and Apple/QCOM will have gains as well so I think they will lead by single digit % IN ST

 

[OneEng2]

The outlook is that the performance gap with the Apple M-series CPUs keeps widening, right? Those are also due another node jump, and the compounded annualized performance growth rate over say 2023-2027 doesn’t seem to be even close to Apple’s - or am I underestimating the clock • ipc improvements?

Apple achieves higher ST performance through:

1) Largely ignoring MT performance
2) Single die vs multi-chip-module
3) Higher performance and more expensive lithography node.

M4 and M5 are both on N3E while Zen 5 is on N4P. M4 and M5 are specifically designed for high performance, low power single thread while Zen 5 is a "Server First" design which can scale up to 192 cores and be fed by a butt ton of memory channels in a modular MCM design.

It always comes back to the engineering concept of "you don't get something for nothing".

 

[Meteor Late]

In mobile doubt and Apple/QCOM will have gains as well so I think they will lead by single digit % IN ST

I am not commenting about leading, Apple already leads in st, I am talking about the margin widening, that's what I don't think will happen. Apple is not exactly showing huge gains in general. I expect the margin between Apple M4 and Zen 5 to be more or less maintained with M6 vs Zen6.

 

[Meteor Late]

Mainstream yes, anything with margins is N2p though.

Which parts would be N2P? I would think something like Medusa Point is a part with margins, like Strix Point is, would that use N2P?

 

[Josh128]

I am not commenting about leading, Apple already leads in st, I am talking about the margin widening, that's what I don't think will happen. Apple is not exactly showing huge gains in general. I expect the margin between Apple M4 and Zen 5 to be more or less maintained with M6 vs Zen6.

Cinebench 2024:
M4 Max 177 1t
285K 145 1t
9950X 139 1t

Apple is currently 27% ahead in CB 2024 ST vs Zen 5. Gap will probably close quite a bit with Zen 6 vs M5, as Zen 6 will have full node advantage, but revert back to the ~25% or so advantage for M6 if that uses N2 or A16.

 

[511]

Apple is currently 27% ahead in CB 2024 ST vs Zen 5. Gap will probably close quite a bit with Zen 6 vs M5, as Zen 6 will have full node advantage, but revert back to the ~25% or so advantage for M6 if that uses N2 or A16.

Zen 6 will not have a node advantage cause M6 on N2 exists and the gap won't be this large maybe around ~10-15%>

 

[poke01]

Cinebench 2024:
M4 Max 177 1t
285K 145 1t
9950X 139 1t

Apple is currently 27% ahead in CB 2024 ST vs Zen 5. Gap will probably close quite a bit with Zen 6 vs M5, as Zen 6 will have full node advantage, but revert back to the ~25% or so advantage for M6 if that uses N2 or A16.

In the Mac Studio it scores 186-190 ST in CB 2024 due to better cooling and it reaching the 4.5GHz clock and sustaining it.

M5 Max would be >190. Looking at Geekbench 6 and 5 results it looks like Apple beefed up FP even more than M3 to M4.

 

[inquiss]

Which parts would be N2P? I would think something like Medusa Point is a part with margins, like Strix Point is, would that use N2P?

Server, desktop, desktop replacement is n2 class. Bulk mobile is n3 class.

 

[Josh128]

In the Mac Studio it scores 186-190 ST in CB 2024 due to better cooling and it reaching the 4.5GHz clock and sustaining it.

M5 Max would be >190. Looking at Geekbench 6 and 5 results it looks like Apple beefed up FP even more than M3 to M4.

View attachment 132299

But muh 7 GHz!! lol, yeah that is a hell of a gap. It would take a 7GHz boost with +10% IPC in 2024 to make 187. Thats not happening, so it looks like the gap will be widening. I didnt know M6 was coming on N2 next year as well.

Zen 5's 139@5.7GHz translates into 174 if you give it +10% IPC in this application and 6.5GHz, which I think is already pushing realistic expectations as to what Zen 6 can deliver.


**EDIT: This chart is labeled as CB R23, but appears to show R24 scores.

 

[LightningZ71]

I thought mobile had three classes: Mobile LP, Mobile HP and Desktop replacement. Mobile LP was N3P monolithic, Mobile HP was N3P Monolithic with an N2 CCD possibly attached, and Desktop Replacement was essentially the desktop processor in mobile packaging like current.

 

[OneEng2]

Which parts would be N2P? I would think something like Medusa Point is a part with margins, like Strix Point is, would that use N2P?

The common speculation and rumor (especially in this forum) is that everything Zen 6 will be on N2 (and some saying N2P which I haven't figured out how that is possible for a 2026 launch) except for a nebulous "bargain laptop" market.

My personal guess/speculation is that this is not correct.

It would make sense for server and workstation to be on N2 (not N2P) while desktop and laptop remained on N3P for cost savings.

It is possible that higher end desktop parts (that still command really good margins) would be N2, but now you have a situation where you are creating 12c CCD's for desktops on 2 different processes .... which seems like a waste.

The defining factor IMO will be if Intel's processors deliver or not. If AMD can (as they do today) maintain superior performance from a less expensive node, then that would be the best path.

If Intel has a winner with their next gen release (and there is already confirmation as I understand it that these will be on N2 and 18A) then AMD may need N2 in the desktop and laptop to compete at the high end.

All of this would have needed to be worked out at AMD long in advance I believe. Whatever track they have chosen is not going to be easily (or quickly) changed.

 

[Doug S]

Apple achieves higher ST performance through:

1) Largely ignoring MT performance
2) Single die vs multi-chip-module
3) Higher performance and more expensive lithography node.

How does Apple "ignore" MT performance? Yes the Max could have more CPU cores, but it would come at the cost of a weaker GPU or a larger more expensive chip. They're responding to what their customers demand.

Anyway, not having a Threadripper / EpyC / Xeon type chip that's all CPU without "wasting" space on GPU, NPU, display controllers and so forth is not increasing their ST. It isn't as if their P cores are too large to make a chip like that if they wanted, and their peak 1T power is less than AMD/Intel so they certainly have the power budget.

Not sure what you even mean with #2. Both AMD and Intel use chiplets, and have some designs where they closely couple LPDDR5X. How are those different than what Apple is doing. And yes Apple is using the best node they have access to. Intel was right alongside them with N3B, I didn't see them competing on ST though. AMD has deliberately chosen hang back on nodes, it isn't Apple's fault they've been cheap in the past. They're on board with N2 though so you won't have that excuse for much longer, though I'm sure you'll find another one!

 

[itsmydamnation]

What i find interesting with all the zen cores, is AMD in effect doesn't chase high IPC at the expense of overall server socket performance. What i mean by that is they actually have a quite small OOE engine in all the Zen CPU's relative to the CPU's they are compared to. AMD spends its core xtor budget in efficiently getting data/ops in and out of the Core.

Having a large OOE engine means more bandwidth pressure to memory, if you arent as efficient in terms of bytes of data into the core per retired op then at large core counts you would see regressions unless you then spent even more xtor budget/power on the memory sub system.

 

[adroc_thurston]

They're on board with N2 though so you won't have that excuse for much longer, though I'm sure you'll find another one!

yeah they still have skinnier cores with server-focused caching strategy. next.

 

[poke01]

yeah they still have skinnier cores with server-focused caching strategy. next.

doesn’t Qualcomm manage similar to Zen area but yeah it comes with a trade off. Skinny cores are not made for high IPC, low frequency.

Apple does manage to get high IPC with lower frequency compared to the competition so at least the fat is used well.
I hope this is what Intel is going for with Unified Core either skinny cores or a fat core thats actually fat for a reason and not cause it’s bad design.

 

[itsmydamnation]

doesn’t Qualcomm manage similar to Zen area but yeah it comes with a trade off. Skinny cores are not made for high IPC, low frequency.

Apple does manage to get high IPC with lower frequency compared to the competition so at least the fat is used well.
I hope this is what Intel is going for with Unified Core either skinny cores or a fat core thats actually fat for a reason and not cause it’s bad design.

How wide a core has a relation but not the sole driver of area. So it's not that amd isn't spending area but they aren't spending it on core width or OOE resources in the same way ost of there competitors do.

 

[OneEng2]

How does Apple "ignore" MT performance? Yes the Max could have more CPU cores, but it would come at the cost of a weaker GPU or a larger more expensive chip. They're responding to what their customers demand.

Anyway, not having a Threadripper / EpyC / Xeon type chip that's all CPU without "wasting" space on GPU, NPU, display controllers and so forth is not increasing their ST. It isn't as if their P cores are too large to make a chip like that if they wanted, and their peak 1T power is less than AMD/Intel so they certainly have the power budget.

Not sure what you even mean with #2. Both AMD and Intel use chiplets, and have some designs where they closely couple LPDDR5X. How are those different than what Apple is doing. And yes Apple is using the best node they have access to. Intel was right alongside them with N3B, I didn't see them competing on ST though. AMD has deliberately chosen hang back on nodes, it isn't Apple's fault they've been cheap in the past. They're on board with N2 though so you won't have that excuse for much longer, though I'm sure you'll find another one!

Apple cores are not made to scale like Zen 5 cores are (192c). As you point out, it isn't a design flaw in anyway, it is simply a design decision for a different market.

The bigger point is that M4 having higher IPC than Zen 5 does not mean it is a better design, only that it had a different design target. Many imagine all Apple would have to do to best Turin/Venice in DC would be to put a bunch of M5 cores together. This is incorrect.

What i find interesting with all the zen cores, is AMD in effect doesn't chase high IPC at the expense of overall server socket performance. What i mean by that is they actually have a quite small OOE engine in all the Zen CPU's relative to the CPU's they are compared to. AMD spends its core xtor budget in efficiently getting data/ops in and out of the Core.

Having a large OOE engine means more bandwidth pressure to memory, if you arent as efficient in terms of bytes of data into the core per retired op then at large core counts you would see regressions unless you then spent even more xtor budget/power on the memory sub system.

I think it is strategic and intentional. If you could take over 1 market in computing, DC would be the one you would want most to win over as it has the highest margins.

Also, with the exponentially rising cost of node shrinks and the corresponding increases in wafer costs, the use of chiplets is a necessity for profit (and yields). Monolithic designs are unrivaled in their efficiencies at lower core counts, but given the minimal transistor density increases we are looking at from here to eternity, chiplet designs is a necessity.

Apple has a different design constraint AND a higher cost ceiling that still allows a monolithic design to rule the day in their market.

 

[poke01]

Also, with the exponentially rising cost of node shrinks and the corresponding increases in wafer costs, the use of chiplets is a necessity for profit (and yields). Monolithic designs are unrivaled in their efficiencies at lower core counts, but given the minimal transistor density increases we are looking at from here to eternity, chiplet designs is a necessity.

I don’t think tablet chips need chiplets, the Mx Pro/Max chips might use chiplets.

 

[OneEng2]

I don’t think tablet chips need chiplets, the Mx Pro/Max chips might use chiplets.

Tablet chips are no different when it comes to maximizing profit by increasing yields with small chiplets vs a large monolithic design.

Additionally, chiplets allow the non-core logic to be created on a less expensive process node.

What chiplets don't do in a laptop market is provide higher performance than a monolithic design does.

Interesting to hear that the PRO/Max chips might use them though!

 

[basix]

Having a large OOE engine means more bandwidth pressure to memory, if you arent as efficient in terms of bytes of data into the core per retired op then at large core counts you would see regressions unless you then spent even more xtor budget/power on the memory sub system.

Not sure if a large OOE will really degrade performance, sounds illogical. At least for server, where peak clock-rate is not a factor (because much lower what the core actually can do). It might not yield in many performance gains because you choke it elsewhere. But a large OOE can hide memory bottlenecks because of extended reorder capabilities. That will not work for all applications, but some. In the end, performance gets determined by a factor of IPC * Frequency. If a wide OOE cannot clock that high, it might still deliver the same performance and therefore memory pressure. But you have to spend more, because the chip area gets bigger. But it might be more efficient, because it clocks lower. So there you have it, the intricate balance of PPA.

I agree with your point, that a fat core might be useless when memory system and data fabric cannot support it. But that could be the cool thing with Zen 6, it removes those memory bottlenecks by a vast amount:
- Lower latency CCD interface
- Higher bandwidth CCD interface
- Increased total L3$ capacity
- Higher DRAM bandwidth

And with that in place, being less memory bound, you can add a larger engine in the core without being hamstrung.

 

[Doug S]

Tablet chips are no different when it comes to maximizing profit by increasing yields with small chiplets vs a large monolithic design.

Additionally, chiplets allow the non-core logic to be created on a less expensive process node.

What chiplets don't do in a laptop market is provide higher performance than a monolithic design does.

Interesting to hear that the PRO/Max chips might use them though!

Apple's "tablet chips" (either the base M in iPad Pro or an iPhone SoC in the rest) aren't all that large so the yield benefit would be marginal. Thanks to their prepayments to TSMC Apple is not capacity constrained so there's little reason to change their monolithic ways on those smaller chips.

If they do go chiplet on the higher end I wonder how much of that would be yield and how much would be to handle Apple's internal server builds. If they want to build some "standard" servers they want lots of CPU cores and no GPU cores. If they want to build "AI" servers they want lots of GPU cores and few CPU cores. Couple that with needing Pro, Max and Ultra (and maybe the ever rumored/dreamed of/hoped for level above Ultra) for their retail units and at some point chiplets make more sense.

They will have more silicon they have to place - they've got the modem, and the wifi/BT chip. That's more stuff that could be integrated on chip (at least the non RF parts) but while that makes sense for wifi/BT since everything has it maybe they'd prefer the modem integration happens as a chiplet - since that's obviously never going to become standard across all their products. So if the A series does end up going chiplet it would probably be driven by the increase in area from adding modem, wifi and BT and the added complexities in binning on that stuff (i.e. you can use iPhone chips with a bad modem in a wifi only iPad, but you can't use a chip with bad wifi or BT for anything)