Question Zen 6 Speculation Thread

[Tuna-Fish]

oh I was way off. I thought it meant high IPC with low clocks. Apologies.

Superscalar means "can execute more than one operation at the same time", and OoO means "can execute operations out of strict program order".

 

[moinmoin]

Going back on track, I hope the rumours about AMD separating core designs for each segment are true for Zen6.

So far the core design used in desktop aside for monolith APUs has been designed for servers. For Zen 6 it seems desktop may get cores designed for mobile instead even for chiplet MCM chips.

But if Strix Halo is showing what's to come high end mobile will be faster than desktop AM5 since premium mobile chips can afford to support more memory channels than supported on AM5.

 

[SteinFG]

Just a wild guess: If Zen 5 CCD from Strix Halo (5nm?) , and Zen 6 CCD from Medusa Halo (3nm?), and Zen 6 CCD from Medusa Ridge (3nm?), are interchangable within the same IO die (like Zen 2/3 and 4/5 on desktop were), There's a chance that AMD can make "Zen5+" of sorts, on desktop: Take the IO die from Zen6 Medusa Ridge, and attach Zen 5 Strix Halo CCD to it. No new parts required, just reusing existing ones. Would be like a cheap version of Zen 6, since it wouldn't use 3nm Zen 6 CCDs.

all of this is just a made up thing in my head, based on absolutely nothing.

 

[igor_kavinski]

Expecting sensible discourse from a new µArch thread 16+ months out from release is a fools errand.

Just watch and enjoy the crazy train 😂

At least now we know to dismiss any claims of <10% IPC gains for Zen 6, with prejudice. If AMD delivers more, good for them and we can consider it a bonus but keeping our expectations to <=10% IPC will ensure that we don't get disappointed or burn unnecessary energy fantasizing about benchmark scores we'll never get to see upon product launch.

 

[FlameTail]

At least now we know to dismiss any claims of <10% IPC gains for Zen 6, with prejudice. If AMD delivers more, good for them and we can consider it a bonus but keeping our expectations to <=10% IPC will ensure that we don't get disappointed or burn unnecessary energy fantasizing about benchmark scores we'll never get to see upon product launch.

Th slides didn't say anything about clock speeds.

Let the Zen6 = 6.6 GHz hype train begin!

 

[FlameTail]

Just a wild guess: If Zen 5 CCD from Strix Halo (5nm?) , and Zen 6 CCD from Medusa Halo (3nm?), and Zen 6 CCD from Medusa Ridge (3nm?), are interchangable within the same IO die (like Zen 2/3 and 4/5 on desktop were), There's a chance that AMD can make "Zen5+" of sorts, on desktop: Take the IO die from Zen6 Medusa Ridge, and attach Zen 5 Strix Halo CCD to it. No new parts required, just reusing existing ones. Would be like a cheap version of Zen 6, since it wouldn't use 3nm Zen 6 CCDs.

all of this is just a made up thing in my head, based on absolutely nothing.

Very interesting. But what's the difference between Granite Ridge CCDs and Strix Halo CCDs? Would they be meaningfully superior so as to warrant making a Zen5+ generation out of it?

 

[SteinFG]

Very interesting. But what's the difference between Granite Ridge CCDs and Strix Halo CCDs? Would they be meaningfully superior so as to warrant making a Zen5+ generation out of it?

No difference, just a new IO die with (potentially) higher memory throuput and lower latency.

 

[branch_suggestion]

No difference, just a new IO die with (potentially) higher memory speed support and lower memory latency.

It uses USR PHYs between the IOD and CCD, similar tech as RDNA3, several times more interconnect bandwidth and lower latency.
And double the memory bus, and 32MB MALL.
Strix Halo is a preview of Zen 6 platform improvements, and it kinda has to show major gains across some apps vs GNR or AMD is in a real pickle.

 

[igor_kavinski]

Let the Zen6 = 6.6 GHz hype train begin!

Chasing frequency helped Intel a lot, didn't it? 🙄

I think frequency scaling is dead.

THE. END.

Engineers/architects need to get more creative.

 

[yuri69]

Strix Halo is a preview of Zen 6 platform improvements, and it kinda has to show major gains across some apps vs GNR or AMD is in a real pickle.

The only problem is, AMD always picks the dirt cheap solution. I still refuse to believe they will use something really advanced for cheapo CPU (e.g. 6c $280 SKUs).

 

[adroc_thurston]

use something really advanced

InFO is very cheap, been used in phones for eons.
It's a volume question.

 

[gdansk]

Zen 6 is looking like early 2027 right now.

According to who?
The same people who told you Zen 5 would be a Conroe moment.

 

[Jan Olšan]

According to who?
The same people who told you Zen 5 would be a Conroe moment.

But that was a good news whereas this would be a bad news. You know how it goes... 😱

 

[soresu]

Superscalar means "can execute more than one operation at the same time", and OoO means "can execute operations out of strict program order".

IIRC out of order is why CPUs need a branch predictor?

 

[soresu]

The same people who told you Zen 5 would be a Conroe moment.

Silly notion.

Obviously Zen1 is AMD's Conroe moment as it's predecessors based on Bulldozer were their Pentium 4.

To call Zen5 their Conroe moment is to imply that Zen1-4 was a dumpster fire period of µArch design which is manifestly untrue.

 

[soresu]

Engineers/architects need to get more creative.

From the dual decoders in Zen 5 and the triple decoders in Skymont they already are.

 

[soresu]

Let the Zen6 = 6.6 GHz hype train begin!

I'm less interested in silly clock frequencies they can manage in 1 -> a few cores as more reasonable frequencies they can manage very efficiently at dozens of cores together under load.

That's where the meat and potatoes of DCC and server scaling lies.

 

[poke01]

why can’t AMD/Intel design a 10-wide decoder instead of these 2x4 and 3x3 ones?

 

[FlameTail]

why can’t AMD/Intel design a 10-wide decoder instead of these 2x4 and 3x3 ones?

X86 decoding is much harder than decoding on ARM, I suppose.

FYI, Lion Cove has a unified 8 wide decoder.

 

[adroc_thurston]

why can’t AMD/Intel design a 10-wide decoder instead of these 2x4 and 3x3 ones?

x86 decoding costs kinda explode when you go bigger.

 

[gdansk]

why can’t AMD/Intel design a 10-wide decoder instead of these 2x4 and 3x3 ones?

Intel does have a 6-wide decoder in Golden Cove and 8-wide in Lion Cove.
But apparently the area needed to do this grows more than linearly with decode width whereas for the fixed-length RISC instructions it isn't too bad and they don't even need to guess where instructions start and end at all.
And still x64 decoding takes longer so they add more decoding pipeline stages to break the work into multiple steps and add micro-op cache to reduce the energy cost associated with repeatedly decoding the same instructions into micro-ops. Some ARM designs have a micro-op cache but apparently not the fastest ones.

 

[soresu]

why can’t AMD/Intel design a 10-wide decoder instead of these 2x4 and 3x3 ones?

My guess would be changing design strategies to compete with ARM server SoC core-a-palooza.

Not sure whether it's better more for area or power, but certainly both have to be on their mind.

 

[soresu]

I wonder if shifting to the x64 only "X86-S" spec will make it easier to design wider decoders without splitting them up to several narrower ones.

 

[adroc_thurston]

I wonder if shifting to the x64 only "X86-S" spec will make it easier to design wider decoders without splitting them up to several narrower ones.

Oh it's not amd64-only, it just throws the legacy init bits out.

 

[gdansk]

I wonder if shifting to the x64 only "X86-S" spec will make it easier to design wider decoders without splitting them up to several narrower ones.

It doesn't look like it. But it should reduce the amount of required tests a bit.