Question Zen 6 Speculation Thread

[Mahboi]

Remarkable how the mood has shifted so seismically.

Why, only a few months ago we were talking about how Zen5's 40% 1T improvement would make it the undisputed leader of ST performance, totally annihilating the competition and put AMD in the lead for years to come!

Would love to be a little mouse to climb into Kepler's head and see how he came to that >40% conclusion.

https://twitter.com/x/status/1821239878233026589

Apparently AMD lied bold faced. Which if true, is very concerning after RDNA 3. The amount of straight up lies is making things difficult with them.

 

[DisEnchantment]

Mehh... shillicon gang. Pranking MLID and stuff, seems they are no better. Wrong on every damn thing being launched recently. Claimed they were right on some obscure crap which never existed on any roadmap.
I would spent as much thought on it as I would with a random video from RGT's DOMINATING updates on every possible launch from NV, AMD et al

 

[CouncilorIrissa]

Would love to be a little mouse to climb into Kepler's head and see how he came to that >40% conclusion.

https://twitter.com/x/status/1821239878233026589

Apparently AMD lied bold faced. Which if true, is very concerning after RDNA 3. The amount of straight up lies is making things difficult with them.

They "extrapolated" 32% 1t gains from Turin 96C being 50% faster than Genoa 96C in SPECint rate N at +25% power.

The tweet is mostly about the Computex presentation I think.

 

[Thibsie]

Remarkable how the mood has shifted so seismically.

Why, only a few months ago we were talking about how Zen5's 40% 1T improvement would make it the undisputed leader of ST performance, totally annihilating the competition and put AMD in the lead for years to come!

Well, looks a lot like the mood in the Qualcomm thread, huh ?

 

[okoroezenwa]

Well, looks a lot like the mood in the Qualcomm thread, huh ?

Nah. FlameTail is making sure the hype train continues there 🤭

 

[MadRat]

The consumer can override the power saving for performance by voiding warranty. Zen5 literally is a power savings boost by design at launch. There is plenty of untapped performance to release higher performance down the road with future products. This stuff is rinse-repeat at AMD. Literally we are reliving the Zen2 experience.

 

[marees]

What is the latest on zen 6 ?

16x p core ccd with 3d v cache ??
Or
8x p core ccd with 3dv cache + 16x c core spam ??

& now that AMD has started releasing laptop APUs first, will they optimize p-core for client & c-core for servers ???

 

[marees]

It would seem straightforward to either stick with monolithic like Strix Point and move to N3e. On N3e, they can finflex the P cores and the C cores appropriately and also add on the speculated MALL cache. With the MALL cache at 16-32 MB, a single speed bin increase on the LPDDR5X ram could support 20CU of RDNA3.5 quite well. That's just two additional WGPs. The next Kraken could grow to 12CU and keep the same core arrangement, but double the L3 in the ccx.

This would make a good steam deck 2, I guess

 

[soresu]

Kepler L2 speculated that the reason for rb delay for 2027 was because desktop Zen6 used LPDDR6, and LPDDR6 LPCAMM modules won't be available until 2027....

Delaying for actual manufactured memory is not necessary as long as the standard spec is published and the IO of the SoC follows that spec.

Unless LPDDR6 is literally the only standard it supports, which would be insane for AMD to do for a brand new standard.

 

[soresu]

What is the latest on zen 6 ?

16x p core ccd with 3d v cache ??
Or
8x p core ccd with 3dv cache + 16x c core spam ??

& now that AMD has started releasing laptop APUs first, will they optimize p-core for client & c-core for servers ???

I'm seriously hoping that the hi end desktop (non TR) platform goes up to 32C.

After 5-6 years on 16C max it's about time it had a serious uptick.

I'd definitely pay £1,200-£1,300 for it simply for CPU RT/PT, fluid sim and software video encoding MT perf.

 

[CakeMonster]

I'd love more than 16 cores but I seriously don't think its very important on desktop in the next ~3-4 years (Z5 and Z6). Though, if there is very little IPC gain (which has made up for more cores in lots of MT apps since Z2) I might change my mind.

 

[soresu]

I'd love more than 16 cores but I seriously don't think its very important on desktop in the next ~3-4 years (Z5 and Z6). Though, if there is very little IPC gain (which has made up for more cores in lots of MT apps since Z2) I might change my mind.

It's not about what is important in terms of AMD's own goals, it's about what competitors offer and whether AMD can offer the same or better.

If Intel just load up their Zen6 era SKUs with moar cores a la the oft praised Skymont then AMD will be left without much choice but to pump up the bass.

 

[Glo.]

Would love to be a little mouse to climb into Kepler's head and see how he came to that >40% conclusion.

https://twitter.com/x/status/1821239878233026589

Apparently AMD lied bold faced. Which if true, is very concerning after RDNA 3. The amount of straight up lies is making things difficult with them.

He always could've been mislead by his sources.

 

[Mahboi]

He always could've been mislead by his sources.

His source is AMD, so...yes?

 

[Glo.]

His source is AMD, so...yes?

Intel, in the first place.

 

[marees]

His source is AMD, so...yes?

Probably an engineering partner for AMD

So Kepler has to interpret the info into what will be the outcome in real applications

(I mean the GPU could boost to 4ghz in factory but doing that in a game in a reasonable power budget !!??)

 

[FlameTail]

Unless LPDDR6 is literally the only standard it supports, which would be insane for AMD to do for a brand new stankard

Its wouldn't be unexpected at all for it to support LPDDR6 only. LPDDR6 is quite unique, and supporting LPDDR5X or DDR6 from the same memory controller is going to be a pain.

 

[soresu]

and supporting LPDDR5X or DDR6 from the same memory controller is going to be a pain

It wouldn't be the first time AMD had supported more than one standard from the same controller.

IIRC Deneb/Phenom II supported both DDR2 and DDR3.

 

[static shock]

I will bet the Medusa Ridge performance: 60% faster at same clock than Zen5 on SPECint rate-1. Doubled L2 and L3 sizes.
Same dual 4-wide decode plus same 6FPU 6ALU, 2nm TSMC. IoD is 3nm TSMC. IPC gains are from digging IPC on this wide ALU digging better IPC at FPU. I bet on AMD widening less this time and digging more IPC. Zen5 diagram already shows how wide and huge the IPC uplift must have been on Zen5.

Launch at Q1/26

 

[Doug S]

It wouldn't be the first time AMD had supported more than one standard from the same controller.

IIRC Deneb/Phenom II supported both DDR2 and DDR3.

DDR3 was a simple evolution of DDR2, same electrical signaling but they doubled the external data rate and lowered the voltage. There were a few other changes but it would have been pretty simple to support both.

LPDDR6 on the other hand is easily the biggest evolution between two DRAM standards, whether DDR or LPDDR. It isn't even the same channel width - going from 16 to 24 bits per controller. Not sure how you could make one controller work for both, without wasting a bunch of area when the controllers are operating in LPDDR5X mode.

AMD has a separate IOD, it would be WAY easier to design two IODs and have some SKUs use one and some use the other. Some might argue that will lead to confusion, but only people buying CPUs and building their own PC will have to know or care about the difference. The average Joe buying a Dell won't care whether it is sold with DDR5, LPDDR5X or LPDDR6.

 

[soresu]

Rembrandt also supported DDR5 and LPDDR5.

 

[soresu]

Something also to bear in mind.

Decoupling memory IO to its own die means that they can have memory controller design on a different schedule to the CPU core µArch.

If you are all assuming that Zen6 desktop is coming later than mobile and server anyway then a dual standard mem controller wouldn't exactly be a huge stretch.

 

[eek2121]

That’s because current AMD designs rely on high frequencies. I want to see AMD design a M1 clone for Zen. Big L2 cache and low frequency and high IPC, it would sell so much. It would make the Steam Deck so good. I wonder if such a design is possible with x86. Cause you have to remember ARM/Apple cores are also much wider than x86.

I feel some people really don’t understand what market segments are. Apple has a big die that costs a ton of money to make. Due to the fact they focus on premium devices AND the fact they profit off the entire system, they can afford to pay more. AMD has to design their chips to scale from under $200 and up, and they only make money off the CPU itself (user is not guaranteed to buy other components). Therefore they use smaller, high frequency dies. They also have to deal with the fact that users still think that “more ghz is better”.

AMD knows where the optimum balance is for PC users and I think they’ve got it right.

Note that they also want to do this with their GPUs to an extent.

 

[poke01]

I feel some people really don’t understand what market segments are. Apple has a big die that costs a ton of money to make.

Apart from the Max die(which I agree AMD cannot do for client or can it? Strix Halo...) the M Pro and base M chips are not big at all.
If we take the M2 and M2 Pro which are on N5P, their total die size is respectively is 153.22mm² and ≈259mm². Note the M2 Pro has a bigger GPU.
If we take the M4 which is N3E, the die size is 166.37mm² and this is the node future Zen6 APUs will be on and AMD will likely have a laptop APU around that area too.

Meanwhile Strix Point has a die size of 232.5mm² on the N4P node. Its got nothing to do with cost, its just a different design philosophy and one that will be useful in laptops/handhelds.

https://hubweb.cn/apple-silicon/chip-m/

 

[inquiss]

I feel some people really don’t understand what market segments are. Apple has a big die that costs a ton of money to make. Due to the fact they focus on premium devices AND the fact they profit off the entire system, they can afford to pay more. AMD has to design their chips to scale from under $200 and up, and they only make money off the CPU itself (user is not guaranteed to buy other components). Therefore they use smaller, high frequency dies. They also have to deal with the fact that users still think that “more ghz is better”.

AMD knows where the optimum balance is for PC users and I think they’ve got it right.

Note that they also want to do this with their GPUs to an extent.

AMDs GPU game seems to be to make all of the units as small as possible and at some point leverage that and their ciplet tech to makes GPU that is bigger than what Nvidia can provide. Whether that happens or not...they seem to get cancelled