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Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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uzzi38 said:
I mean I didn't actually outright say that it was an LP island on here... but yeah, I guess the secret's out? I really don't want to be the one to spill the beans on some of the details of it though, so the only thing I'm going to say is the comparison to A10 fusion was intentional. Especially wrt scheduling.

cc @Gideon because I see you just asked in the other thread.
Click to expand...
Wait. You’re telling me my out-of-left-field guess had merit?! :openmouth:
Saylick said:
Just a total dart throw, but one thing it would be nice to see AMD do is to match Intel in reducing their idle power consumption via the use of a low power core. I recall there being an AMD patent a ways back where they had the cache of a big core be shared with a small core or something to that effect where in essence the workload could be passed between the cores without much penalty. If Zen 6’s IOD uses N4X then you could make that small core pretty power efficient by using those uLVT transistors and shutting down the compute die. Plus, the use of Infinity Link or whatever AMD calls it to connect the compute die to the IOD may allow for the small core approach to work. Given that Adroc hinted that Zen 6 desktop is more mobile-like than ever, this idea is not too far fetched in my opinion.

Edit: found the article.
videocardz.com

AMD patents a task transition method between BIG and LITTLE processors - VideoCardz.com

AMD “big.LITTLE” aka heterogeneous computing in Ryzen 8000 series The next decade will no longer be dictated by the number of cores, but rather the processor’s fabrication node, packaging method, and power effciency. A big role will also be played by heterogeneous architectures. Later this year...
videocardz.com videocardz.com
Click to expand...
 
Saylick said:
Wait. You’re telling me my out-of-left-field guess had merit?! :openmouth:
Click to expand...
Yeah, that's where I went back to to follow the full trail.
Your suggestion, the mention of A10 Fusion vs Bionic, later other hints by Uzzi or Adroc...
You all added a piece and it seems to make sense. AMD looks like they're gearing up for an LP core as one of the founding parts of Zen 6. And Strix Halo may be the first piece to test it. An early look at Zen 6 mobile...
 
moinmoin said:
You got the additional information on your own already by now, but just for clarification again: That's wasn't true during the Bulldozer years. There were those infamous cores called construction cores (Bulldozer Piledriver, Steamroller, Excavator) that made AMD uncompetitive during those years, and the low power cat cores (Bobcat, Jaguar, Puma) that at least kept AMD in the games consoles business if nothing else.


That's with OS visible cores where the scheduler may be too stupid avoiding moving tasks to incompatible cores.

There had been an interesting AMD patent that talks about very small cores just implementing fast basic instructions (essentially only for I/O without actual computing) that otherwise cause an exception with the task then being moved to the full core, all of that being completely hidden from the OS. (I'd have to search for the patent, but we discussed it several times in the past.)

The issue about that is that I recall Microsoft recently making it a rule that it's no longer allowed to hide such cores from Windows so such hardware if realizable may end up not being used under Windows anyway.
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What motivation would Microsoft have to butt in here? Security? Why do they care what cores their software runs on? If someone replies, please avoid unnecessary Microsoft bashing.
 
Actually if they're going for an LP Core, what's the likely basis for it?
Taking the Cats into a modern version?
Shrunken down Zen?
Completely new design from scratch?

Makes the compact Zen cores a bit redundant...but just a bit.
 
Now the missing links:
moinmoin said:
There had been an interesting AMD patent that talks about very small cores just implementing fast basic instructions (essentially only for I/O without actual computing) that otherwise cause an exception with the task then being moved to the full core, all of that being completely hidden from the OS. (I'd have to search for the patent, but we discussed it several times in the past.)
Click to expand...
I mentioned it in this thread before actually:

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The older discussion about it:

Discussion - Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

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forums.anandtech.com

moinmoin said:
The issue about that is that I recall Microsoft recently making it a rule that it's no longer allowed to hide such cores from Windows so such hardware if realizable may end up not being used under Windows anyway.
Click to expand...
@adroc_thurston previously mentioned in this thread that Microsoft now mandates that all cores be visible to the OS:

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Ghostsonplanets said:
I'm not sure if monolithic Strix and Kraken will feature Z5 LP cores. They're probably for Halo only.

Yes, SP is 4x Z5 + 8Z5C. KRK is either 4P + 4E or binned 2P + 4E.
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They are for Halo only, or so Adroc said.
So yes those 4 extra cores over Point have a very high chance of being just LP cores, if it has to be 4 of them as you said.

Dunno if KRK will have an advanced packaging like this for a low end part, I doubt they'll put LP cores there first. Halo seems to be really an early peek into Zen 6's packaging and lineup differentiations.
 
adroc_thurston said:
crikey, the chief e-beggar leaked the funny bit out.

It's Zen5 derivative but I dunno how lobotomized it actually is.
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From an engineering and TTM standpoint, this does make more sense than building off a dedicated new Cat core. Z5/Zen cores is ISA compatible, power efficient at lower levels and very small already. So it's the perfect choice.

It's a smart approach that only AMD could do. Intel P cores are too big and inefficient at low power for them to be turned into LP/E cores. So that leaves Intel with the mismatched ISA hybrid cores strategy.
 
Mahboi said:
Dunno if KRK will have an advanced packaging like this for a low end part, I doubt they'll put LP cores there first. Halo seems to be really an early peek into Zen 6's packaging and lineup differentiations.
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Oh, you misunderstood me. Kraken is replacing PHX/HWK in mainstream laptops (<$999/$800). Its the same strategy as Strix Point: Mixing Zen 5 Classic cores with Zen 5 Dense cores.
 
adroc_thurston said:
They aren't.
Question is, what survived the lobotomy.
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No one said it has to be a Zen 5 derivative, right? Wouldn’t a Zen 4 core also work? As long as it has the same ISA and can more or less execute the same instructions, even if it’s at half rate, it should be fine, no? Cutting the FP block is generally a low hanging fruit if you want to reduce the core size. It doesn’t mean it cant support AVX-512 still.
 
Ghostsonplanets said:
AMD developed the Cat lineage until before Zen launch. By then, the market for these type of x86 cores was becoming smaller and smaller due to Arm competition, failure of x86 at Mobile markets and AMD difficulties in general.
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The cats were built by a tiny team, that managed to massively outpetform expectations.

The reason cat core development ended was not about the market, it was that someone (iirc Samsung? Not sure and I don't have time to check it) poached the entire team whole from AMD. This was before the Zen success and when AMD had money issues.
 
If I am understanding what is being discussed correctly, it is not a core at all - just like a filter on top of regular Zen 5 cores that can carry out a subset of instructions in a power efficient manner without waking up the full core.

If this is the case, why would this be exclusive to Halo? Perhaps because Zen 5C doesn't really benefit?
 
Tuna-Fish said:
The cats were built by a tiny team, that managed to massively outpetform expectations.

The reason cat core development ended was not about the market, it was that someone (iirc Samsung? Not sure and I don't have time to check it) poached the entire team whole from AMD. This was before the Zen success and when AMD had money issues.
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Wait, the Austin M series team was derived from the AMD Cat team? Huh, that's actually surprising. Had no idea, thanks for sharing.

I wonder if some of them came back to AMD after the disbanding of Samsung Custom program.
dhruvdh said:
If I am understanding what is being discussed correctly, it is not a core at all - just like a filter on top of regular Zen 5 cores that can carry out a subset of instructions in a power efficient manner without waking up the full core.

If this is the case, why would this be exclusive to Halo? Perhaps because Zen 5C doesn't really benefit?
Click to expand...
Think Intel like. A P core, an E core and a LP Core Complex Island at the SoC.

Except that in AMD case, unlike Intel, it's using the same cores and ISA. Just with different PPA targets:

Zen 5 Classic = Performance
Zen 5 Dense = Area and power efficiency
Zen 5LP = Extreme area savings and absolute power efficiency.
 
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