Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[adroc_thurston]

the RAM, memory and latency is the bigger bottleneck.

Ughhh depends on the workload.

 

[Ghostsonplanets]

Credits to Uzzi

Already being discussed on another thread, but mlid leaked the one of the reasons why Adroc thinks Halo is the most cool part of Zen 5 line-up: Strix Halo features LP Core island.

This is what Branch_Suggestion and Uzzi alluded at last week.

Strix Halo is basically a preview of Zen 6: Advanced Packaging + Bigger SoC die with IGP and LP Island.

 

[Mahboi]

LP Core "island" meaning...there's a part of the die that's specifically designed for low power usage and shuts off the rest of the die on idle?

 

[Ghostsonplanets]

LP Core "island" meaning...there's a part of the die that's specifically designed for low power usage and shuts off the rest of the die on idle?

Aye. I assume it's a 4 - 6 Core Island to avoid Intel MTL situation where the LPE are too few to even run anything while the Compute Die idle.

And I don't think these are "Zen 5" cores proper. I assume this is a specifically designed new Cat like core for very low power, unlike LPE which are rehashed E cores. Scheduling would be a mess, but maybe there are some ways to work around it?

 

[Mahboi]

Aye. I assume it's a 4 - 6 Core Island to avoid Intel MTL situation where the LPE are too few to even run anything while the Compute Die idle.

And I don't think these are "Zen 5" cores proper. I assume this is a specifically designed new Cat like core for very low power, unlike LPE which are rehashed E cores. Scheduling would be a mess, but maybe there are some ways to work around it?

Very interesting, but the latter part is a bold assumption.

AMD has been making one core, and only one core, since forever. It's baked into their business model: make a 8 core CCD, cut it to 6 when you have to, put two CCDs when you have to, put 8/12 CCDs on server chips.
I somehow doubt that they'd build a different core for lower power, unless I'm mistaking what you mean by "Cat like".

 

[uzzi38]

Credits to Uzzi

Already being discussed on another thread, but mlid leaked the one of the reasons why Adroc thinks Halo is the most cool part of Zen 5 line-up: Strix Halo features LP Core island.

This is what Branch_Suggestion and Uzzi alluded at last week.

Strix Halo is basically a preview of Zen 6: Advanced Packaging + Bigger SoC die with IGP and LP Island.

I mean I didn't actually outright say that it was an LP island on here... but yeah, I guess the secret's out? I really don't want to be the one to spill the beans on some of the details of it though, so the only thing I'm going to say is the comparison to A10 fusion was intentional. Especially wrt scheduling.

cc @Gideon because I see you just asked in the other thread.

 

[Gideon]

Aye. I assume it's a 4 - 6 Core Island to avoid Intel MTL situation where the LPE are too few to even run anything while the Compute Die idle.

And I don't think these are "Zen 5" cores proper. I assume this is a specifically designed new Cat like core for very low power, unlike LPE which are rehashed E cores. Scheduling would be a mess, but maybe there are some ways to work around it?

It would be wonderful to see a a cat-core derivate solution!

cc @Gideon because I see you just asked in the other thread.

Yeah i was just thinking in the other thread, could it be connected to this patent:

AMD Files Patent for its Own x86 Hybrid big.LITTLE Processor

AMD is innovating its own x86 hybrid processor technology formulated along the Arm big.LITTLE hybrid CPU core topology that inspired Hybrid processors by Intel. Under this, the processor has two kinds of CPU cores with very different performance/Watt bands—one kind focuses on performance and...

www.techpowerup.com

Hopefully something on the igpu side as well, that could drive/refresh a single screen without powering on the full display engine (or something).

 

[Ghostsonplanets]

I mean I didn't actually outright say that it was an LP island on here... but yeah,

You had said it was related to the A10 example and the last week discussions about AMD patents. Also, there is a old image about AMD roadmap (I think it's from MLID too?) that also features "low power Core options" for Zen 5. So I kind connected the dots.

At first I actually thought it was a handheld mode for Strix Halo. But that didn't made any sense😂

 

[soresu]

Yeah i was just thinking in the other thread, could it be connected to this patent:

AMD Files Patent for its Own x86 Hybrid big.LITTLE Processor

AMD is innovating its own x86 hybrid processor technology formulated along the Arm big.LITTLE hybrid CPU core topology that inspired Hybrid processors by Intel. Under this, the processor has two kinds of CPU cores with very different performance/Watt bands—one kind focuses on performance and...

www.techpowerup.com

Isn't that basically Phoenix 2?

Hopefully something on the igpu side as well, that could drive/refresh a single screen without powering on the full display engine (or something).

Pretty sure there's a Displayport feature that does something like refresh a display without actually requiring a continuous signal if nothing new is being sent.

A great power saving feature for battery constrained platforms, but it's probably not implemented desktop side.

 

[Abwx]

It would be wonderful to see a a cat-core derivate solution!

If the I/O die is 6nm based then why designing anything new since they can straightforwardly use RMB Zen3+ cores layout wich is precisely using 6nm..?.

 

[Ghostsonplanets]

6nm? I'm pretty sure the rumor is that CCDs are N4X while SoC is N3E, no?

For Strix Halo I mean

 

[Philste]

Aye. I assume it's a 4 - 6 Core Island to avoid Intel MTL situation where the LPE are too few to even run anything while the Compute Die idle.

Is it that or did Intel do something else wrong? Ofc 2 little Cores aren't much, but they are about skylake in performance and 2 skylake Cores should be able to run a web browser. Yet the battery life of MTL is only good with deactivated WIFI. I feel like the problem is something different than pure lack of performance of those Cores.

I would also say 4 Cores is the maximum amount of cores in such an LP Island. I don't see them putting 6 Cores in there, I also doubt they will develop a separate uArch just for that. But ZEN5c would be far too powerful for something like that.

Still the 2 most likely options for me would be: -2×ZEN5c (chance of it being ZEN4c).
-4× off-shelf ARM Core (A720 or whatever oder the current middle Performance Line)

 

[uzzi38]

Is it that or did Intel do something else wrong? Ofc 2 little Cores aren't much, but they are about skylake in performance and 2 skylake Cores should be able to run a web browser. Yet the battery life of MTL is only good with deactivated WIFI. I feel like the problem is something different than pure lack of performance of those Cores.

Lets just say there's a very good reason why Intel are moving on to 4 LP-E cores so quickly (Lunar Lake, Panther Lake etc).

 

[Abwx]

6nm? I'm pretty sure the rumor is that CCDs are N4X while SoC is N3E, no?

For Strix Halo I mean

Anyway they dont need to design anything new since they have enough cores designs at disposal, a 3nm porting take much less time than designing something that would have to pass all validation steps with all inherent respinings, at 3nm they could even use Zen 4 FI without eating much area.

 

[DisEnchantment]

It would be wonderful to see a a cat-core derivate solution!

I hope they go for something much more purpose built, for instance, compared to the likes of QCM that would be extremely overkill.

Arm SoC vendors obviously have the experience from mobile side.
There is something called AOP (always On Processor) which remains alive when the entirety of the SoC goes into full power off.
DRAM goes into a mode called self refresh and basically everything is dead. Some SoCs can keep the some sections of the DSP alive (also called NPU ) which can receive audio triggers to wake up the SoC and handle voice commands from sleep. Not all SoCs can do this but support for it is there in Android for instance.

Again here you can understand why NPU exists as separate power island from the GPU. It can remain alive by itself and receive audio triggers. The optimizations here can be so wild that the sampling frequency can be even brought down.

This AOP is very basic core, can handle some IO and read sensors etc., and update some data in the memory regions it is allocated from the DRAM pool. When wake conditions are met, the SoC just resumes normally without losing anything. The AOP just hands over everything to the SoC

Looking at things like these it is obvious why the likes of Apple and QCM will have the superior battery life for mobile devices, because they came from a different world compared to PC.

This is far far more efficient that the sleep states defined by ACPI which is more tailored for PC use cases.

16.1. Sleeping States — ACPI Specification 6.4 documentation

 

[Mahboi]

What's a cat core?

 

[Ghostsonplanets]

What's a cat core?

It's a shorthand to Bobcat. Bobcat was a line of small, ultra low power cores that AMD developed for the then nascent and rising Tablet/Netbook markets, with focus on 1 - 10W designs. The most famous implementation of Bobcat line of cores was on the consoles PS4 and Xbox One.

AMD developed the Cat lineage until before Zen launch. By then, the market for these type of x86 cores was becoming smaller and smaller due to Arm competition, failure of x86 at Mobile markets and AMD difficulties in general.

So when people talk about a Cat core, they mean a new core that is focused on ultra low power like the Bobcat were.

 

[Mahboi]

Thank you Ghost, I was about to go and search every SE for "meaning for the CAT abbreviation" and "meanings of CAT acronym".
Easily the thing that filters me the most in this industry is still the insane amount of very specific shorthands...

 

[Mahboi]

Incidentally I'd be extremely surprised by a proper low power core from AMD. And I don't buy any notion of mix/matching with ARM.
Their Zen 4c was already offering serious area and some lower power progress.
I would say one of the biggest, by far the biggest actually, unknown about Zen 5 is the potential area reduction and power usage of Zen 5c. It seems to me that AMD has got a big boost from the compact cores, and hasn't had to make the large sacrifices that Intel had to with their e-cores. I don't see them suddenly jumping into designing a new core when Zen 5c comes out. I also wonder about how much more compact can Zen5c be.

Going off the Zen3 Vcache implementation and what Zen4 made of it, Zen4 AVX 512 implementation and what Zen 5 will make of it, Zen4c being a first implementation of a compact core and Zen 5c being the second could yield a lot of fruits. I don't know how possible it would be to make a much larger core, have a full width AVX 512 implementation, and have the compact core be very compact and a lower power user...seems like a catch 22 to me, but if Halo has a 2 or 4 Zen5c cores that are tuned to use very low power, I wouldn't be surprised at all.

 

[Ghostsonplanets]

so the only thing I'm going to say is the comparison to A10 fusion was intentional. Especially wrt scheduling.

I'm not too knowledgeable about A10. Neither my little research was anything deep. But what I could find was:



Zephyr small cores are located just beside Hurricane cores, like they're growing out of the big cores. Also, A10 b.l implementation was based on cluster migration were the P cores were the ones that did everything foreground. While the E cores handled idle, background, etc. But the key takeaway (imo) is this:

One thing Apple has emphasized in talking about the A10 is that their design uses a custom designed performance controller to manage the CPU cores and migrate tasks between them.

Emphasis on "custom designed performance controller to manage the CPU cores and migrate tasks between them"

So this tells me (A rather shallow analysis tbf) that the Zephyr E Cores weren't OS aware but rather through an intermediate layer were the controller gave and received feedback from the OS and migrated tasks accordingly (I'm probably dead wrong here, but I'm not too knowledgeable about Apple).

So, going back to AMD implementation and comparison with A10, this is what I think:

- Unlike Zephyr, they'll be located outside of the CCD, at the SoC die.
- They'll be Cat like cores that aren't "proper Zen 5".
- Unlike Intel, where they leave to Windows scheduler and Thread Director to schedule things to LPE cores accordingly (And fail most of the time), AMD will be doing a custom hardware solution, like Apple, that "bypass" the OS scheduling and force things unto the Low Power Island.

This is a very outlandish idea and I don't even know if it's feasible. Maybe some kind of firmware layer in-between or something. But the idea should be that the Low Power Island will be akin to phones always on processor and handle low power/compute tasks and idling situations while the CCDs are at a minimum power state possible, basically "shutdown".


I don't think my idea make any sense, but worth the shot🤣

 

[leoneazzurro]

It's a shorthand to Bobcat. Bobcat was a line of small, ultra low power cores that AMD developed for the then nascent and rising Tablet/Netbook markets, with focus on 1 - 10W designs. The most famous implementation of Bobcat line of cores was on the consoles PS4 and Xbox One.

AMD developed the Cat lineage until before Zen launch. By then, the market for these type of x86 cores was becoming smaller and smaller due to Arm competition, failure of x86 at Mobile markets and AMD difficulties in general.

So when people talk about a Cat core, they mean a new core that is focused on ultra low power like the Bobcat were.

It was not only Bobcat in that line of products, there were also the Puma and Jaguar, which were all... cats. So all these cores were called the AMD "Cats" family.

 

[CouncilorIrissa]

[mention]Ghostsonplanets[/mention] oh god, what have you done?
Watch this guesswork make it into wccftech news section in a matter of hours.

 

[JustViewing]

So, going back to AMD implementation and comparison with A10, this is what I think:

- Unlike Zephyr, they'll be located outside of the CCD, at the SoC die.
- They'll be Cat like cores that aren't "proper Zen 5".
- Unlike Intel, where they leave to Windows scheduler and Thread Director to schedule things to LPE cores accordingly (And fail most of the time), AMD will be doing a custom hardware solution, like Apple, that "bypass" the OS scheduling and force things unto the Low Power Island.

This is a very outlandish idea and I don't even know if it's feasible. Maybe some kind of firmware layer in-between or something. But the idea should be that the Low Power Island will be akin to phones always on processor and handle low power/compute tasks and idling situations while the CCDs are at a minimum power state possible, basically "shutdown".


I don't think my idea make any sense, but worth the shot🤣

The cores must have same instruction set architecture, otherwise AMD will end up like Intel disabling features of big core. For IO die, they can use a low power 4 core APU added with more IO paths.

 

[moinmoin]

AMD has been making one core, and only one core, since forever.

You got the additional information on your own already by now, but just for clarification again: That's wasn't true during the Bulldozer years. There were those infamous cores called construction cores (Bulldozer Piledriver, Steamroller, Excavator) that made AMD uncompetitive during those years, and the low power cat cores (Bobcat, Jaguar, Puma) that at least kept AMD in the games consoles business if nothing else.

The cores must have same instruction set architecture, otherwise AMD will end up like Intel disabling features of big core. For IO die, they can use a low power 4 core APU added with more IO paths.

That's with OS visible cores where the scheduler may be too stupid avoiding moving tasks to incompatible cores.

There had been an interesting AMD patent that talks about very small cores just implementing fast basic instructions (essentially only for I/O without actual computing) that otherwise cause an exception with the task then being moved to the full core, all of that being completely hidden from the OS. (I'd have to search for the patent, but we discussed it several times in the past.)

The issue about that is that I recall Microsoft recently making it a rule that it's no longer allowed to hide such cores from Windows so such hardware if realizable may end up not being used under Windows anyway.

 

[Mahboi]

You got the additional information on your own already by now, but just for clarification again: That's wasn't true during the Bulldozer years. There were those infamous cores called construction cores (Bulldozer Piledriver, Steamroller, Excavator) that made AMD inconmpetitive during those years, and the low power cat cores (Bobcat, Jaguar, Puma) that at least kept AMD in the games consoles business if nothing else.

Yes I'm rethinking after reading all of Ghosts' posts and the patent.
It's a difficult thing to take into consideration. Ghost and Uzzi and others have given extremely clear hints but I find it difficult to believe that Strix Halo is going to be the first thing to use the first LP core of AMD since Jaguar. This just adds so many criteria to AMD's mobile strategy, or perhaps even general strategy.