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Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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It's quite possible Zen 7 is still N3 family while N2 is reserved for more expensive and higher margins EPYC products.

We'll probably be seeing some slowdown in the adoption of bleeding edge nodes for consumer products in the coming years.

Edit: Now that I think about it, with Z6 unifying Mobile and Desktop into a single thing, it doesn’t make sense for Z7 to be on N3 as Mobile is a deeply competitive space. Definitely a brainfart moment of mine. Z7 should also be a 28 product, so N2 BSPD should be a mature node by then.
 
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Tuna-Fish said:
You seem very confused. nVidia 40 series did not use N4P for the very simple reason that they entered production nearly a year before N4P was available. They used 4N, which was one of the early 5nm processes, and not anywhere near the most advanced 5nm silicon. 4NP was developed later, using knowledge accumulated during 3N development, and is both faster and more economical to manufacture. TSMC is pushing all clients to use N4P, like they earlier pushed everyone to use N6, using favorable prices. Blackwell is using N4P, and so will Zen5, and frankly every other newly developed 5nm-class product.
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I am glad we have someone who works for TSMC here. Tuna Fish, please enlighten us all with TSMC slides and not those published by anandtech or some other tech review site. Please explain the difference between N4 and 4N. After that we will get into N4P. Nvidia 40 series cards were on a 4N something variant that is more efficient than standard 4N.
AMD has already said many times that Zen 5 Ryzen CPU's will start out on N4. The refresh of Zen 5 sometime in 2025 will be on a 3nm variant.
 
Hans Gruber said:
I am glad we have someone who works for TSMC here. Tuna Fish, please enlighten us all with TSMC slides and not those published by anandtech or some other tech review site. Please explain the difference between N4 and 4N. After that we will get into N4P. Nvidia 40 series cards were on a 4N something variant that is more efficient than standard 4N.
AMD has already said many times that Zen 5 Ryzen CPU's will start out on N4. The refresh of Zen 5 sometime in 2025 will be on a 3nm variant.
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It seems you know the values, based on your claim that N4P is much less efficient that N3. Please provide the details that led you to such claims.
 
maddie said:
It seems you know the values, based on your claim that N4P is much less efficient that N3. Please provide the details that led you to such claims.
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I never said anything about N4P. I said that N4 is 10-15% less efficient than N3. The only real TSMC performance numbers that I have stated come from TSMC press releases. The TSMC charts listed in this thread are from anandtech (main page tech review site) and contain a lot of question marks. They do not know what the performance numbers are. I said it would be nice if TSMC would publish all of their performance differences from one process to another.

Several months about I got attacked for talking about the performance differences between TSMC silicon processes on the same node. People believed all 7nm silicon was the same. All 5nm silicon was the same and that Nvidia hyped up their customized process for PR reasons. Forum members believe that TSMC customizes silicon for their customers and that the process is the same for all. This is not true. N5 is the baseline for 5nm. The first and standard performance. N3 is the first and baseline 3nm process by the same regard. After making thousands of wafers, TSMC perfects each process node. The yields are improved which means each wafer has more chips that are totally functional and not waste. I am not a lithography expert.

Apple has said they were disappointed there was no uplift with N3 (3nm) other than substantial power efficiency gains. The power efficiency gains were offset by Apple increasing the voltage to improve performance going from 5nm silicon to 3nm silicon. When there is a node shrink 7nm>5nm, customers have come to expect an uplift in performance outside of their chip design that comes directly from the fab process. With 5nm, that uplift does not exist like it had with 7nm. With N3 (3nm), there is no uplift in performance according to Apple.

N4P is probably TSMC's way of giving their customers something while they wait for N3P because of the difficulties with 3nm. Nvidia used 4N-something (40 series cards) which is more efficient and better than the standard N4 silicon. N4 silicon is the 5nm variant of what N6 is to the 7nm process. My guess is that N4P is even closer to the standard N3 in efficiency and performance. Probably within 5-7% performance and efficiency compared to N3.

On a side note. Nvidia bought a ton of TSMC silicon that they prepaid for. After the crypto crash and the covid craze ended. TSMC would not refund Nvidia for their huge silicon purchase. My guess is that Nvidia is using N4P (Blackwell) because of all the silicon they purchased from TSMC a few years back. It would seem TSMC gives Nvidia the right to use any silicon they want on the 5nm process node. All you have to do is see how a 4060 sips power. The same can be said of the 4070. Very impressive silicon on the 5nm TSMC process.
 
It was stated here, some days back that ... 'Strix Halo' would probably come on N3E ... and that N3P was the planned node for Zen6 ...

🙂
 
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Matters less than ever. And especially for desktop where they have 230W to play with.

But TSMC wants everyone on improved N4 variants so they probably are.
 
Kolifloro said:
I was stated here, some days back that ... 'Strix Halo' would probably come on N3E ... and that N3P was the planned node for Zen6 ...

🙂
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I think you are right. The Turin server chips will come out with N3 from launch. The Zen 5 refresh in 2025 is supposed to be on either N3 or N3E. The N3P stuff has yet to be released. Sometime later this year and that will be the premium silicon through at least 2025.
 
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