Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Kepler_L2]

According to MLID Zen 5 will arrive late because of Mainboard issues. He says that the announcement will probably be around computex with availability later...does not sound good to me. I thought april was kinda save...

There are no "next-gen boards" (and why would they be called 800-series when current boards are 600-series?)

Also DDR5-8000, 2400 FCLK, X3D launching day one and 8+16 SKUs are pure fantasy from him.

 

[Glo.]

IPC is the only way companies will be able to extract performance on smaller nodes.

If AMD was able to do it on N4 - its a good showcase of what is coming on smaller nodes, albeit with lower density gains than before.

 

[adroc_thurston]

IPC is the only way companies will be able to extract performance on smaller nodes.

no lol, clocks aren't going anywhere.

If AMD was able to do it on N4 - its a good showcase of what is coming on smaller nodes, albeit with lower density gains than before.

AMD is aiming for chunggus IPC because they have a dense core to sell where it matters. Which demands very high IPC to clap the likes of Neoverse V et al.

 

[Kaffeekenan]

That's not the real number, the real number sounds like pure bs.
It just showcases the general direction of Z5 and future AMD cores (chunggus IPC bumps to make dense a very viable option across data center in general, not just cloud in particular).

Soooooooo just to clarify this 100%. You are talking HIGHER and not way LOWER or something and that's why it sounds like bs, right?

 

[Hitman928]

It's easy. Zen 5 has roughly 45% higher IPC than Zen 4 and can hit 5.2 GHz single core boost. That would give Zen 5 roughly 32% more overall single thread performance over Zen 4 which is where that number really comes from. Done.

(I don't actually have any idea, just playing around with numbers).

 

[Glo.]

AMD is aiming for chunggus IPC because they have a dense core to sell where it matters. Which demands very high IPC to clap the likes of Neoverse V et al.

Sounds expensive.

In transistors and die size, especially.

 

[adroc_thurston]

You are talking HIGHER and not way LOWER or something and that's why it sounds like bs, right?

Yea.

It's easy. Zen 5 has roughly 45% higher IPC than Zen 4 and can hit 5.2 GHz single core boost. That would give Zen 5 roughly 32% more overall single thread performance over Zen 4 which is where that number really comes from. Done.

naa.

Sounds expensive.

In transistors and die size, especially.

Leadership isn't free.
You've seen MI300.
But again, AMD CPU teams are very good at IPC:Cac and IPC:area metrics.

 

[Glo.]

Leadership isn't free.
You've seen MI300.
But again, AMD CPU teams are very good at IPC:Cac and IPC:area metrics.

There is no free lunch anymore. Even here, on this front.

 

[adroc_thurston]

There is no free lunch anymore. Even here, on this front.

There hasn't been a free lunch on IPC front since like P6/K7 era.
Either way, AMD teams are very good at what they do.

 

[H433x0n]

It's easy. Zen 5 has roughly 45% higher IPC than Zen 4 and can hit 5.2 GHz single core boost. That would give Zen 5 roughly 32% more overall single thread performance over Zen 4 which is where that number really comes from. Done.

(I don't actually have any idea, just playing around with numbers).

There’s an ancient cinememe leak from anandtech’s favorite leaker (MLID) showing a dual socket 64C Turin ES sample and the results suggest the nT uplift isn’t 40%+.

 

[Timorous]

how do I even say that without sounding schizo?

So you are saying Zen 5 is giving us over Zen 4 what Zen gave us over Bulldozer?

I mean it would explain why Mike Clark was super duper excited about it back when Ian interviewed him but as you say, that kind of claim is so out there it needs to be seen to be believed.

 

[adroc_thurston]

So you are saying Zen 5 is giving us over Zen 4 what Zen gave us over Bulldozer?

Perf-wise maybe, efficiency no since we're not jumping to FinFETs.
Still, they should maintain or beat this ratio.

I mean it would explain why Mike Clark was super duper excited about it back when Ian interviewed him but as you say, that kind of claim is so out there it needs to be seen to be believed.

yeah the thing's a bit nuts, way above everyone's expectations really, so you gotta see SIR and workload performance with your own eyes to believe it.

 

[yuri69]

IPC is the only way companies will be able to extract performance on smaller nodes.

This sounds like the sentiment about the then-upcoming 5nm like two years ago.

 

[adroc_thurston]

This sounds like the sentiment about the then-upcoming 5nm like two years ago.

no, N5 was like the last real go zoomzoom node due to shiny hi-mo fins.
GAA later on maybe, but BSPDN heat sandwich will put somewhat of a limit on what you could do wrt clocks and heat density.

 

[StefanR5R]

[xyz] suggest the nT uplift isn’t 40%+.

As for Genoa-->Turin nT performance progression, it's almost straightforward:

• Modestly improved manufacturing process, wider core, smaller changes to IOD are expected.
• All this should lead to a modest nT performance increase at iso power.
• Multiply this with the fact that max PPT limit per socket will be increased from 400 to 500 W (+25%).

Now we can do the math what sort of nT performance uplift there will be for servers, at iso core count.

 

[branch_suggestion]

I suppose this is confirmation of Z5 being the highest IPC core in the world.
Pretty clear that they have made a major breakthrough on the front end, conveniently that is the one area of the core all leaks have said nothing about.
Only shame is about the SMT yield. The fact the thing clocks comfortably over 5GHz is what will make the ARM boys head scratch.

 

[Saylick]

I suppose this is confirmation of Z5 being the highest IPC core in the world.
Pretty clear that they have made a major breakthrough on the front end, conveniently that is the one area of the core all leaks have said nothing about.
Only shame is about the SMT yield. The fact the thing clocks comfortably over 5GHz is what will make the ARM boys head scratch.

Agreed. Should hopefully finally dispel the belief that x86 cannot scale as wide / have the same IPC as flagship premier ARM cores.

 

[adroc_thurston]

Should hopefully finally dispel the belief that x86 cannot scale as wide /

Both it and LNC yeah.
To markedly different results though.

 

[poke01]

Both it and LNC yeah.
To markedly different results though.

Bit like X4 core from ARM being 10 vs A17 Pro being 9 wide and still the A17P is much better.

Design matters and it looks like LNC being a wide core doesn't mean much if performance/efficiency is not up to there.

 

[adroc_thurston]

Bit like X4 core from ARM being 10 vs A17 Pro being 9 wide and still the A17P is much better.

Apple is better because it clocks higher.

 

[poke01]

Apple is better because it clocks higher.

If we compare X4 with A15 which has lower clock, the A15 is still better in IPC. Its just not clock.

AMD design is just better this time around than Intel's

 

[adroc_thurston]

A15 is still better in IPC

It's better IPC than A17p too, FYI.
Clocks cost stuff.

 

[FlameTail]

It would be better if Strix Point (not Halo) has Infinity cache...

https://x.com/Olrak29_/status/1752069416010039299?s=20

 

[FlameTail]

It's better IPC than A17p too,

No

 

[branch_suggestion]

https://x.com/Olrak29_/status/1752069416010039299?s=20

Bodes well for RDNA3.5 clocks then.