Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[adroc_thurston]

Is that what Strix Halo is using

Isn't it pretty obvious.

or are those just standard Zen5 CCDs connected with IFoP?

not suitable for mobile

 

[Joe NYC]

Isn't it pretty obvious.

That's what it looked like, but doesn't it require then some custom Zen5 die.

Because, I am guessing, you don't necessarily need SerDes if the data is routed via Fan Out RDL.

 

[adroc_thurston]

but doesn't it require then some custom Zen5 die.

Well yea.
Gotta start somewhere.

you don't necessarily need SerDes if the data is routed via Fan Out RDL.

Duh.

 

[Joe NYC]

The opposite.
dGPs share their design with server and client lives in a FOWLP ghetto.

Isn't it possible that in 2-3 years, the costs of the silicon bridges vs. FOWLP will become the same, or even lower?

 

[A///]

cIOD

client io die was redesigned for zen 4 was it not? why redesign again for zen 5.

 

[A///]

No, Zen 4 was between 11 and 13% geomean, depending on whether you count gaming workloads in the average or not. 19% geomean (spec 1T workload) was Zen 2 -> Zen 3.

I am fairly certain lisa said 19%...

 

[A///]

never mind! it appears my memory of generational uplifts is mixed up.

 

[A///]

let's go 25-30% ipc increase!

 

[adroc_thurston]

the costs of the silicon bridges vs. FOWLP will become the same, or even lower?

no.
FOWLP will be the cheapest option for a while.

 

[Hitman928]

New thread started for IVR discussion if anyone wants to continue it there.

 

[Thibsie]

New thread started for IVR discussion if anyone wants to continue it there.

It goes way over my head but interesting nonetheless.
Thank you.

 

[Ajay]

Linky: https://forums.anandtech.com/threads/integrated-voltage-regulators-discussion.2614378/

 

[Joe NYC]

FOWLP will be the cheapest option for a while.

A little boring.

Although I hope TSMC and AMD keep accelerating and growing the Hybrid Bond capacity, the reality money being thrown on CoWoS has to be, to some extent, derailing / slowing down HB.

I hope there is some re-useability of the packaging equipment that does CoWoS, that it can also do HB.

 

[adroc_thurston]

A little boring

Boring is good (for mainstream).

the reality money being thrown on CoWoS has to be, to some extent, derailing / slowing down HB.

No, very different tools and capacity.

 

[Tuna-Fish]

I think, looking at how the chiplets are connected in the cancelled Navi4x, this is how AMD will connect chiplets in all of their products.

Maybe later. But as I understand it, zen5 mostly changes things inside the cores themselves, the uncore and everything downstream of it is basically as in zen4. Zen6 then brings system-level changes.

 

[adroc_thurston]

Maybe later. But as I understand it, zen5 mostly changes things inside the cores themselves, the uncore and everything downstream of it is basically as in zen4. Zen6 then brings system-level changes.

Correct!
Think of Zen5 as Conroe and Zen6 as Nehalem.

 

[gdansk]

Correct!
Think of Zen5 as Conroe and Zen6 as Nehalem.

Zen 6 SMT4 confirmed

 

[yuri69]

Maybe later. But as I understand it, zen5 mostly changes things inside the cores themselves, the uncore and everything downstream of it is basically as in zen4. Zen6 then brings system-level changes.

The Zen 6-based server Venice is rumored to be the thing to look forward viewed from the overall nextgen architecture PoV. Zen 5 is still using the current design.

 

[igor_kavinski]

Correct!
Think of Zen5 as Conroe and Zen6 as Nehalem.

Zen 6 gonna need DDR6? Or will AMD release it both on AM5 and AM6?

 

[adroc_thurston]

Zen 6 gonna need DDR6?

That's later.

Or will AMD release it both on AM5 and AM6?

AM6 is a fair bit later.

 

[Joe NYC]

The Zen 6-based server Venice is rumored to be the thing to look forward viewed from the overall nextgen architecture PoV. Zen 5 is still using the current design.

Any idea what socket will Zen 6 have? It would not surprise me if the socket grows some more, beyond SP5.

SH5 socket is bigger, but apparently, it has no local memory pins...

 

[adroc_thurston]

SH5 socket is bigger,

No it's the same SP5 with different keying (no DDR pins, more serial I/O, more power etc).

 

[Joe NYC]

No it's the same SP5 with different keying (no DDR pins, more serial I/O, more power etc).

Interesting. If the pins are different then keeping the same socket is good only for heatsink / cooling. Mobo will have to be different, the whole mobo design will have to be different if it is dropping DDR pins / DDR slots.

Can AMD fit any local memory or HBM inside the socket? Or way more cache?

 

[adroc_thurston]

Can AMD fit any local memory or HBM inside the socket?

Looks tight so no.

Mobo will have to be different, the whole mobo design will have to be different if it is dropping DDR pins / DDR slots.

which is why it's called SH5, not SP5.

 

[Joe NYC]

Looks tight so no.

which is why it's called SH5, not SP5.

I see, I think I confused myself here. I was under the impression that SH5 was physically different (and bigger) then SP5.

So is then Venice SP5, SH5 or something else?