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Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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adroc_thurston said:
They won't, you're going straight to Granite Ridge.
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There is still a lot of time left in H2.

In this generation, 7900x3d can absorb GCDs with some defective cores. So if there is a 7600x3d, it would mean that AMD has a plentiful capacity and is disabling cores to increase volume of sales.
 
naukkis said:
It's not a trivial problem. There's two different voltage regulators in series where both of them can affect voltage rise times.
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The two voltages regulators in serial are the external usual VRMs wich is indeed in serial with the integrated LDOR, that s all.

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naukkis said:
And it's documented, AMD have used years system that regulates core clock by actual delivered voltage - it's absolutely needed scheme to drive voltage margins down. AMD LDO is natural evolution step on that regulation scheme - after shaving voltage margins for all cores they also shaved those per core basis.
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Of course that CPU frequency and voltage leval are tied, but as i said it s way easier to supply the core with a PWM filtered voltage than with a straight continuous voltage whose value is controled by a pure analog loop.

With a PWM voltage you can raise the voltage very quickly while a pure analog setting loop is much slower because you have to introduce a DAC whose output voltage must be integrated before driving the Pfets, it doesnt make sense at all since the PWM signal that is sent to a sigma/delta DAC input can drive directly the Pfet and then integration will occur at the Pfet outputs.

Beside you ll have to implement capacitors at the Pfets output whatever the circuitry.
 
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Abwx said:
The two voltages regulators in serial are the external usual VRMs wich is indeed in serial with the integrated LDOR, that s all.

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Of course that CPU frequency and voltage leval are tied, but as i said it s way easier to supply the core with a PWM filtered voltage than with a straight continuous voltage whose value is controled by a pure analog loop.

With a PWM voltage you can raise the voltage very quickly while a pure analog setting loop is much slower because you have to introduce a DAC whose output voltage must be integrated before driving the Pfets, it doesnt make sense at all since the PWM signal that is sent to a sigma/delta DAC input can drive directly the Pfet and then integration will occur at the Pfet outputs.

Beside you ll have to implement capacitors at the Pfets output whatever the circuitry.
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I think it would be helpful if this discussion had its own thread. It more of a discussion about the best options for CPU/SoC power regulation rather than being entirely Zen specific (though it started that way). And it’s taking up a fair bit of space in this thread that we could otherwise waste on pointless rumors from MILD. IMHO.
 
Ajay said:
I think it would be helpful if this discussion had its own thread. It more of a discussion about the best options for CPU/SoC power regulation rather than being entirely Zen specific (though it started that way). And it’s taking up a fair bit of space in this thread that we could otherwise waste on pointless rumors from MILD. IMHO.
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At least we can be sure that this is one thing that got about unchanged since Zen 1 and it will extend to Zen 5 as well, in a way that s on topic whatever the Zen iteration...

Other than this there s about no news about Zen 5 set apart the alleged numbers from RTG and in the waiting of MLID s take on the thing, in the waiting if you have something new on the subject, even a meager bone, that would be welcomed...
 
Abwx said:
At least we can be sure that this is one thing that got about unchanged since Zen 1 and it will extend to Zen 5 as well, in a way that s on topic whatever the Zen iteration...

Other than this there s about no news about Zen 5 set apart the alleged numbers from RTG and in the waiting of MLID s take on the thing, in the waiting if you have something new on the subject, even a meager bone, that would be welcomed...
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What does radeon technology group have to do with mlid?
 
naukkis said:
It's not a trivial problem. There's two different voltage regulators in series where both of them can affect voltage rise times. And it's documented, AMD have used years system that regulates core clock by actual delivered voltage - it's absolutely needed scheme to drive voltage margins down. AMD LDO is natural evolution step on that regulation scheme - after shaving voltage margins for all cores they also shaved those per core basis.
Click to expand...

Finally had time to at least briefly look through the patents posted. It looks like AMD is using a fairly typical dLDO at its core for the individual core voltages, but obviously with some twists/enhancements. Much of my post will probably be a recap of things already discussed, but just wanted to make sure we're on the same page.

As already pointed out, they are not using a single regulated output for multiple reasons. They have the system level VR, which is high efficiency, large area, and slow. The system level VR will regulate to the highest needed voltage of any core/block. From there, the individual cores/blocks are provided with an additional regulated voltage provided through the dLDO. AMD is calling this a distributed regulation scheme. The main purpose/innovation of their patents is actually related to this distributed regulation scheme, rather than the dLDO design. This scheme, as outlined, has several benefits, not the least of which includes being able to be very area efficient and the ability to scale extremely well, even to provide effective VR for massive GPUs. The dLDO does suffer in efficiency when there is a large voltage drop required. The worst case scenario here would be when one core is running at full boost, requiring a high voltage, and the other cores are at idle, only requiring a low voltage.

The dLDOs supplying the cores at idle will tank in efficiency due to having to provide a large voltage drop from the system supplied voltage which is required to be high due to the boosting of the single core. With that said, from a system level view, the low efficiency of the dLDOs in this situation is not very impactful because the current draw in those dLDO's will be a small fraction of the system power consumption anyway. In other words, yes, you are getting bad efficiency from the dLDOs, but the magnitude of the power consumption of those idle cores/dLDOs is so low that you don't care much anyway and you are gaining far more efficiency by allowing the idle cores to have their own low voltage lines to begin with. The dLDOs supporting high frequency/voltage cores should be very efficient due to the low voltage drop required as well.

As for the dLDO itself, as I mentioned, it looks like AMD is using a fairly standard dLDO with some tweaks. For a quick recap, a dLDO works fairly similarly to the analog LDO @PJVol posted a schematic diagram of. However, rather than an error amplifier, you would have an ADC and control signal block. Rather than a PFET being used as a common source amplifier, you would have an array of PFET switches. How many switches are turned on in parallel to provide the proper regulated voltage is controlled by the control signal block. AMD is, at least at a high level, using this same topology. They call their ADC a PSM and the control signal block a dLDO controller, but it works the same way.

There are two enhancements AMD has made to this design that I can see from the patent. The first enhancement is that, unlike in a standard dLDO, the PFET switches need not be homogeneous. In other words, they have PFET switches that are designed to give high, medium, or low resistance. This gives them the ability to have finer resolution (more accurate) control over the regulated voltage. The downside is that it makes the control circuitry more complex, but obviously AMD has figured out that the additional overhead in the control logic is worth it. The second enhancement is that they are rolling into the design a voltage droop detector (they call this a fast droop detector) which can bypass the normal control feedback flow and take over the control signals if a big enough voltage droop is detected. This allows AMD to quickly compensate for any large transients in the load (core) current. The cost here is simply the circuitry for the voltage droop detector and then a large MUX which will switch the control signals from regular control to droop scenario control if the voltage droop threshold is reached. I don't imagine this circuitry only has a negative effect on efficiency, but is obviously critical for a robust design.

I think the patents lay out pretty well what AMD is doing and it's a clever design. Basically the engineering trade off is individual core VR efficiency for overall system (SOC) efficiency, area, and scalability (I didn't touch too much on scalability but it is actually a key component of the design and is outlined well in the patents).

Edit: @Ajay, I was typing this out as I had time throughout the morning and didn't see your request before posting. If someone wants to continue to discuss this and wants to make a separate thread, I'll post any replies there instead.
 
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igor_kavinski said:
I think he was referring to this: https://forums.evga.com/Leak-sugges...Ds-Zen-5-Ryzen-8000-series-CPUs-m3610716.aspx

For an ES, those scores are insane.
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oh yes I remember those figures. I thought he meant rtg was leaking info about the cpu side of the company which I found rather interesting for obvious reasons. mr fat pubic hair jabba the hut is as good as mlid, in other words neither are remotely worth listening to until we get close to launch and details leak.
 
This is a very long thread and I've not read all of the posts. For those that have followed it, just wondering:

1. What is the consensus on expected release date of Zen5? Some are claiming 2024Q1, others 2024H2. Is there any actual evidence of one or the other, or just speculation?

2. Are the Zen5 desktop CPUs expected to use only Zen5 cores, or a mix of Zen5 and Zen5C cores like similar Intel desktop CPUs which use performance + efficiency cores?

3. Is there any expectation on Zen5 with regards to power consumption at idle and load? Is it expected to stay roughly at the same levels as on Zen4, or will there be any improvement and if so why?

4. What are the guesstimates with regards to ST and MT performance for Zen5 compared to Zen4?

5. Is there expected to be any update for the IO die with Zen5, with regards to e.g. chip process tech (nm), number if iGPU cores, or similar? With regards to iGPU performance it's way behind corresponding Intel desktop CPUs, so is that situation expected to remain?

Feel free to answer any of the questions, no need to answer all if you don't want to.

One of the reasons for asking is to determine whether it's worth waiting for Zen5 or buying a Zen4 based system hopefully at discount during Black Friday 2023.
 
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Fjodor2001 said:
One of the reasons for asking is to determine whether it's worth waiting for Zen5 or buying a Zen4 based system hopefully at discount during Black Friday 2023.
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The sweet thing is, you can get a nice AM5 mobo and use it with 7600X or a plain 7900 if you want better MT. Then wait for a sale on the Zen 5 and do a drop-in upgrade. No need to keep waiting for Zen 5 as it will be too expensive at launch, unless you are a very patient person and you want AMD to be a few hundred dollars richer.
 
igor_kavinski said:
The sweet thing is, you can get a nice AM5 mobo and use it with 7600X or a plain 7900 if you want better MT. Then wait for a sale on the Zen 5 and do a drop-in upgrade. No need to keep waiting for Zen 5 as it will be too expensive at launch, unless you are a very patient person and you want AMD to be a few hundred dollars richer.
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I know. But usually I don't upgrade that frequently. More like every 5-10 years. Hence the reason for the questions.
 
igor_kavinski said:
I think he was referring to this: https://forums.evga.com/Leak-sugges...Ds-Zen-5-Ryzen-8000-series-CPUs-m3610716.aspx

For an ES, those scores are insane.
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Actually there s something that is not logical in those scores, the 6C and 8C should score a little more than half the 12C and 16C respectively, unless the low core count SKUs are limited to 65W TDP/88W PPT, but still this doesnt explain the higher uplift percentage wise for the 16C comparatively to the 12C assuming they are both at 170W TDP.
 
Fjodor2001 said:
Some are claiming 2024Q1
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Like early Q2 or therein.
Fjodor2001 said:
to use only Zen5 cores
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Yes.
Fjodor2001 said:
Is there any expectation on Zen5 with regards to power consumption at idle and load?
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Same idle with the same PPTs so nothing changes from your POV.
Fjodor2001 said:
What are the guesstimates with regards to ST and MT performance for Zen5 compared to Zen4?
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CHOMGA
Fjodor2001 said:
Is there expected to be any update for the IO die with Zen5
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No it's the exact same Raphael cIOD.
Fjodor2001 said:
or buying a Zen4 based system hopefully at discount during Black Friday 2023.
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Only if it's cheap enough since Zen5 will atomize Zen4 in client particularly well.
 
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