Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[adroc_thurston]

Then what process will that SoC actually use?

N3e.

It won't be small either.

Well it's named -halo for a reason.

Going to be interesting to see if they can get OEMs to really use this versus just throwing on a cheesy nVidia GPU like they are now.

Depends on how much cash AMD is willing to pour to prop the segment into viability.

 

[Joe NYC]

I can agree with more than a single SKU, but will they really go down to 8 cores?
Yes, you could use only a single CCD, but the reason why I am sceptical about that is the existence of Strix Point. That one will have 4 Zen5 + 8 Zen5c cores, so Strix Halo with only a single CCD would be slower in the CPU department.

I see a possible lineup like this:
Strix Halo: 16 Zen5, 40CU RDNA3.5, 256-bit LPDDR5x
Strix Halo: 14-16 Zen5, 36CU RDNA3.5, 256-bit LPDDR5x
Strix Halo: 12 Zen5, 32CU RDNA3.5, 192-bit LPDDR5x
Strix Halo: 10-12 Zen5, 24CU RDNA3.5, 192-bit LPDDR5x
Strix Point: 4+8Zen5(c), 16CU RDAN3.5, 128-bit LPDDR5x
Strix Point: 4+6Zen5(c), 12CU RDNA3.5, 128-bit LPDDR5x
Strix Point: 4+4Zen5(c), 8CU RDNA3.5, 128-bit LPDDR5

8 full Zen 5 cores with their full L3 is more than capable enough for a laptop. The CCD may have a V-Cache option as well.

16 cores would be just for halo effect, just for the longest bar on some MT benchmarks, not for anything super practical.

I think the main point is to integrate dGPU level graphics at lower cost and lower power consumption than adding dGPU.

Let's say for gaming notebooks. 8x Zen 5 cores + full graphics capability would serve a decent sized niche.

 

[Glo.]

8 full Zen 5 cores with their full L3 is more than capable enough for a laptop. The CCD may have a V-Cache option as well.

Product like large APU is not only for laptops.

Its a mobile first design that can scale up, not down. Most of it however will go to laptops, obviously. But use cases for product like Strix Halo are more than just laptops.

If anyone remembers what I was talking about few months ago that there is coming paradigm shift in mainstream computing - those people should know what products like Meteor Lake-P and Strix Halo are for.

 

[Joe NYC]

Yes but it's more SKUs. Annoying.

That is true, but worth it. The cost saving measures of integrating CPU + dGPU + DRAM (from 2 dedicated sets) all into one package should be a good value proposition for OEMs. Should enable them to cut their own design and validation costs and also BOM.

At the same time, it would shift more of the notebook BOM to AMD.

 

[adroc_thurston]

The cost saving measures of integrating CPU + dGPU + DRAM (from 2 dedicated sets) all into one package should be a good value proposition for OEMs

No.
DRAM is whatever.

it would shift more of the notebook BOM to AMD.

Yes which is what they want to avoid.

 

[Joe NYC]

All FP10 parts are 256b.

Is that the name of the new socket?

 

[TESKATLIPOKA]

N3e.

Well it's named -halo for a reason.

If they are willing to use N3e for SoC, then I would expect the same also for the CPU tiles. At least, I am sure this won't be cheap.

 

[Joe NYC]

Depends on how much cash AMD is willing to pour to prop the segment into viability.

Area where AMD needs to improve. AMD may release a leading product in a segment and still not get past 20% market share in the segment where it has a leading product

 

[Joe NYC]

Product like large APU is not only for laptops.

Its a mobile first design that can scale up, not down. Most of it however will go to laptops, obviously. But use cases for product like Strix Halo are more than just laptops.

If anyone remembers what I was talking about few months ago that there is coming paradigm shift in mainstream computing - those people should know what products like Meteor Lake-P and Strix Halo are for.

I agree with that. Most office desktop users can live just fine with Mini PCs powered by mobile CPUs.

I think Strix Halo would fit this market quite well.

 

[TESKATLIPOKA]

8 full Zen 5 cores with their full L3 is more than capable enough for a laptop. The CCD may have a V-Cache option as well.

16 cores would be just for halo effect, just for the longest bar on some MT benchmarks, not for anything super practical.

I think the main point is to integrate dGPU level graphics at lower cost and lower power consumption than adding dGPU.

Let's say for gaming notebooks. 8x Zen 5 cores + full graphics capability would serve a decent sized niche.

I didn't say 8 Zen5 cores won't be capable enough per se, It's more about how would you price It.
What price would you set for 8 Zen5 + 40CU RDNA3.5 vs 12 Zen5 + 32CU RDNA3.5
or 4+8Zen5 +16CU RDNA3.5?
Then there is still the question of how good would 8 Zen5 be against the competition?

 

[Joe NYC]

Yes which is what they want to avoid.

There is more to managing a profitable company than pleasing one GM obsessed analyst at CC (Stacy Rasgon), to the detriment of the company shareholders and customers.

 

[jpiniero]

Product like large APU is not only for laptops.

Its a mobile first design that can scale up, not down. Most of it however will go to laptops, obviously. But use cases for product like Strix Halo are more than just laptops.

Even AIOs these days are IGP only. Strix Halo seems only really suited for gaming laptops. Strix Halo is going to be too expensive for any other segment.

 

[adroc_thurston]

Is that the name of the new socket?

Yes.

then I would expect the same also for the CPU tiles

They don't need to.

AMD may release a leading product in a segment and still not get past 20% market share in the segment where it has a leading product

It's an inherintly niche product, even 5 design wins would be something.

There is more to managing a profitable company than pleasing one GM obsessed analyst at CC (Stacy Rasgon)

Eyyyy Stacy is a cool guy. Shush.

Strix Halo seems only really suited for gaming laptops

No, it's for premium 15/16" thins first and foremost.

 

[Joe NYC]

If they are willing to use N3e for SoC, then I would expect the same also for the CPU tiles. At least, I am sure this won't be cheap.

I think we are at the point of when the Zen 5 CCD is entering volume production in the fabs. Way past the time to make any changes.

The question is if AMD made a dedicated CCD for Strix Halo or just modified some metal layers to be compatible with Fan Our packaging.

I think the likelihood is that this is not a fully redesigned CCD that stripped out the GMI lins from the die area. Most likely just redesigned metal layers, same as what AMD did with Zen 4 for Mi300.

Cost is definitely a concern, for parts that could be on N6. But I think this is AMD trying to create a new segment, and this is just its first implementation. Follow up products may be more fine tuned...

 

[adroc_thurston]

The question is if AMD made a dedicated CCD for Strix Halo

This.
IFOPs go out, USR goes in.

I think the likelihood is that this is not a fully redesigned CCD that stripped out the GMI lins from the die area

It is a redesign (not a new floorplan, just a tiny link swap).

Most likely just redesigned metal layers, same as what AMD did with Zen 4 for Mi300.

Atta, that one does HB with tiny pitches that allows to connect ingest ring SDP directly to the underlying fabric tile.
No can do that with 2.5D pkg.

 

[Joe NYC]

I didn't say 8 Zen5 cores won't be capable enough per se, It's more about how would you price It.
What price would you set for 8 Zen5 + 40CU RDNA3.5 vs 12 Zen5 + 32CU RDNA3.5
or 4+8Zen5 +16CU RDNA3.5?
Then there is still the question of how good would 8 Zen5 be against the competition?

I don't think AMD will be going much below full 40 CUs. 1 vs. 2 CCDs is going to be the main segmentation.

I think 8 Zen 5 CCDs with the strong GPU capability could be the sweet spot for gaming capable notebooks.

 

[A///]

@Joe NYC You still pining away at writing an email to st nicholas/st su for a 16c die for consumer?

 

[Glo.]

I don't think AMD will be going much below full 40 CUs. 1 vs. 2 CCDs is going to be the main segmentation.

I think 8 Zen 5 CCDs with the strong GPU capability could be the sweet spot for gaming capable notebooks.

Strix Halo should compete in GPU perf terms with 4050, 4060 and 4070 laptop GPUs.

So it should yield 3 SKUs.

 

[Joe NYC]

Eyyyy Stacy is a cool guy. Shush.

Integrating DRAM in package would be a nightmare scenario for Stacy, since it would lower GMs. But at the same time increase AMD revenue and EPS, even if AMD can charge only a 5% mark-up on that DRAM.

So good for shareholders, and Lisa is a bigtime shareholder...

 

[Joe NYC]

@Joe NYC You still pining away at writing an email to st nicholas/st su for a 16c die for consumer?

haha, yea, I am going to do some knitting and make a colorful sock for it.

 

[Joe NYC]

This.
IFOPs go out, USR goes in.

It is a redesign (not a new floorplan, just a tiny link swap).

Atta, that one does HB with tiny pitches that allows to connect ingest ring SDP directly to the underlying fabric tile.
No can do that with 2.5D pkg.

That seems like quite a serious effort. For something that will not right away be a volume product.

So, in theory, eliminating GMI / IFoP from both sides can result in some die area savings and those savings alone can pay for Fan Out packaging...

It should have some small to modest improvements in number of areas when it comes to memory accesses, their latency and power overhead.

 

[Glo.]

Even AIOs these days are IGP only. Strix Halo seems only really suited for gaming laptops. Strix Halo is going to be too expensive for any other segment.

Itll be cheaper than implementing Intel and Nvidia GPU combo.

In terms of engineering effort, complexity of the boards, and the product, itself.

So why not use it, even for premium-mainstream products?

 

[Abwx]

So good for shareholders, and Lisa is a bigtime shareholder...

Not the subject of the thread but i think that she got way way too much for the time she s at the helm of AMD, not a good thing if one want a still performing CEO.

For such a reward AMD should be at 50bn yearly revenue at least, wich is far from being the case.

 

[adroc_thurston]

Integrating DRAM in package would be a nightmare scenario for Stacy, since it would lower GMs. But at the same time increase AMD revenue and EPS, even if AMD can charge only a 5% mark-up on that DRAM.

No it's just doing more effort for negligible packaging area gains.

That seems like quite a serious effort

PHY swaps aren't quite that.

So, in theory, eliminating GMI / IFoP from both sides can result in some die area savings and those savings alone can pay for Fan Out packaging...

No you stick a fat PHY in and let it run lowest link states outside of heavy loads.

 

[TESKATLIPOKA]

N3E vs N5 provides 32% reduction in power draw at ISO performance.

This is pretty good If you think about It.
If we say that 7800XT had 225W just for the GPU alone, then 2/3 of units would be 150W, further reducing It by N3e process would result in 102W at 2430MHz.
Then there is still the possibility of higher clocks by fixing what went wrong in RDNA3, It really could end up faster than N22 while consuming a lot less.