Yonah article here on Anandtech Part II

[Betwon]

Originally posted by: dmens
I know it is impossible because I own that chunk of logic on a P6-style uproc in dev, and yeah, I know the historical background too because I read all those design docs as well. Nitpicking about the meaning of x86 wording reveals absolutely zilch about backend operation. Please get the basics from a book or something because I'm not going to explain anything in detail.

I feel that your explanations shows you think it is impossible for CPU not to place the load op into RS?

Or you only think it is impossible for P6?

 

[dmens]

LOL read the thread, we've been talking about P6 only, I've said as much.

 

[Betwon]

Originally posted by: dmens
LOL read the thread, we've been talking about P6 only, I've said as much.

I have asked you a question:
Is a certain model of CPU in Patent 5974523 "Mechanism for efficiently overlapping multiple operand types in a microprocessor" more close to P6 CPU?

I think if you get the basics and own that chunk of RS logic on a P6-style uproc in dev, you can give me a answer: Yes.

You can tell us what is the basics about RS of P6?

 

[dmens]

Yes that is a P6 related patent. If you want to learn about the P6, go read a book or search online, since the P6 is still a popular teaching example. I don't feel like explaining stuff to rude trolls.

 

[Betwon]

Originally posted by: dmens
Yes that is a P6 related patent. If you want to learn about the P6, go read a book or search online, since the P6 is still a popular teaching example. I don't feel like explaining stuff to rude trolls.

Now, you say:Yes.
It is too later.

Patent 5974523 had shown the most important thing--even the detail structure of RS.
That can lead to the correct answer.

In your explanations, You take some mistakes. Do you admit it?

 

[dmens]

I didn't even look at that patent until just now, and that patent only deals with a subset of RS functionality. On top of that, the structure described in the patent is totally irrelevant to the question of load dataflow. So no, everything I said is correct, and you are wrong.

 

[Betwon]

Originally posted by: dmens
I didn't even look at that patent until just now, and that patent only deals with a subset of RS functionality. On top of that, the structure described in the patent is totally irrelevant to the question of load dataflow. So no, everything I said is correct, and you are wrong.

"everything I said is correct, and you are wrong"?

Yes, you are always right, even there are mistakes.

 

[Markfw]

yes betwon, you are wrong ! give it up, and go away, we are all sick of your crap.

 

[Betwon]

Originally posted by: Markfw900
yes betwon, you are wrong ! give it up, and go away, we are all sick of your crap.

Show us an entry of the reservation station to the MOB units.

You only need give a Patent No.

 

[Markfw]

I WILL LET DMENS ANSWER THAT, HE KNOWS, AND YOU DON'T

 

[Betwon]

Originally posted by: Markfw900
I WILL LET DMENS ANSWER THAT, HE KNOWS, AND YOU DON'T

Yes, YOU DON'T KNOW ANY THING ABOUT THIS MATTER.

BUT YOU WILL BE AGAINST THE ONE WHO LET YOU FEEL ANGRY.

 

[Markfw]

"let me feel angry" ? I just know you are an idiot fanboy, thats all. If you want to participate on an english forum, please learn how to speak english.

 

[Betwon]

Originally posted by: Markfw900
"let me feel angry" ? I just know you are an idiot fanboy, thats all. If you want to participate on an english forum, please learn how to speak engrish.

There are really problems for me about how to speak english correctly.

your "engrish".

 

[dmens]

HAHAHA patent number. Sorry, but patents do not reveal cycle accurate pipeline diagrams and detailed protocols. That's for me to know, and you to guess incorrectly, despite all the hints I give. LOL!

 

[Betwon]

Originally posted by: dmens
HAHAHA patent number. Sorry, but patents do not reveal cycle accurate pipeline diagrams and detailed protocols. That's for me to know, and you to guess incorrectly, despite all the hints I give. LOL!

The patent already give the some of detail structure of an entry of RS.
Since you say that it is only a subset of RS. Please show us an entry of the reservation station to the MOB units. Let us be able to find it in some or one patent.

 

[Markfw]

Please betwon, its getting embarassing to read your posts. Please don't post anymore as you continue to demean yourself.

 

[Betwon]

Originally posted by: Markfw900
Please betwon, its getting embarassing to read your posts. Please don't post anymore as you continue to demean yourself.

engrish

 

[IntelUser2000]

WE DON'T KNOW THE EXACT PIPELINE STAGES OF PENTIUM M'S!!!

For all I care, Banias/Dothan/Yonah could be same pipeline stages, and can be anywhere between 11 and 15. Only thing that's sure is that Conroe has 14 stages. Intel has only stated that Banias/Dothan is greater than P6 and less than Netburst in pipeline stages. It could be that Banias has 14 like Conroe will have.

I have heard people saying from their "measurements" its 12. But I heard 13, and I heard as extreme as 17.

Quote from AT: (Link: http://www.anandtech.com/showdoc.aspx?i=1800&p=7)

In the course of designing a processor, you will eventually discover that there are certain speed paths in your CPU that will run either faster or slower than your target clock speed. If you run into paths that run slower than your target clock speed, you're in trouble, since it means that you won't be able to reach the clocks you were hoping to without some sort of a redesign. In most cases, if you find that a path is running faster than your target clock speed (e.g. finding a path capable of running at 2.4GHz on a chip with a 1.6GHz target clock speed) then you're in a very good situation, as it means that there are parts of your chip that have fairly high ceilings. For the Israel design team however, this wasn't the case.

In desktops, we wouldn't need that limitation, and that would be Conroe. 65W TDP Intel is targeting for Mainstream and 80W TDP for Extreme Editions/Servers is quite a lot of room from Yonah's 31W.

 

[IntelUser2000]

BTW, Yonah will have higher TDP variants called "E" series probably standing for "Extreme" that will apparently clock ONE TO TWO clock speed grades higher than the highest "T" series. Highest "T" would be 2.33GHz, so "E" could be 2.5 or 2.67GHz. Now that would be competitive with X2's.