Originally posted by: pm
Originally posted by: fbrdphreak
Mostly right here. More cache != more latency. It is all in how they design/implement the cache. Dothan had 2MB L2, as did the later P4's; but the P4's L2 was much much higher latency.
I'd just add that more cache does usually imply more latency. There's more to the equation than just cache size and latency - how many read/write ports there are, how many ways, what restrictions there are on reading and writing ports, parity/ECC, how the tag compare is performed, how much power the circuit can afford to burn, how big the cache cell is (versus yield and low-voltage operation). But if everything is equal in terms of feature set, then adding more memory to the cache will slow it down either by adding more fan-in to the calculations, or by adding more loading to the cache lines slowing down the evaluate.
Originally posted by: coldpower27
Why does everyone keep saying Conroe have 4 more pipes? Conroe has a 14 stage pipeline. Isn't this only 2 more pipes then Athlon 64, and 1-3 Pipes more then Yonah. If your talking pipeline stages at least.
I believe there is confusion over how many stages the pipeline is (how long the pipeline is), versus how many instructions can be issued (how wide the pipeline is).