Yield challenges in FinFET foundry land

[Arachnotronic]

Am I saying that Intel will be getting late with 10nm? No. What I'm saying is that 10nm is giving them enough headaches to the point they can't commit themselves to a given timeline, and if so the risks of a delay are palpable.

This is a reasonable conclusion. Coupled with Idontcare's insight, I think it's pretty clear that 10nm is proving quite a challenge for Intel.

 

[witeken]

This is a reasonable conclusion. Coupled with Idontcare's insight, I think it's pretty clear that 10nm is proving quite a challenge for Intel.

No one denies that, creating 30nm feature sizes with 193nm wavelengths with immersion lithography and quadruple patterning, yielding 80-90%, sounds ridiculous. No one will be able to pull that of for many years to come, certainly not if and when coupled with III-V/Ge transistor.