Yahooo vhdl coding is fun.

[William Gaatjes]

I have not even begun to scratch the surface and i am already loving VHDL.
It is so much fun to use the xilinx ISE to code for spartan chips.
The simulator i am starting to grasp.

I am learning it for work, but i will be able to make a lot of use from it for the hobby as well. My little droid is becoming slowly a reality.

I am very gappy.
^_^.


It has its advantages to be autodidact. You will end up in the gutter, you are too dumb, i was told more then i enjoyed hearing. Hellspawn. Yet here i am, omen turned anti, anti christ. yep - * - makes +.

 

[Markbnj]

It has its advantages to be autodidact. You will end up in the gutter, you are too dumb, i was told more then i enjoyed hearing. Hellspawn. Yet here i am, omen turned anti, anti christ. yep - * - makes +.

I'll try to understand this later. Maybe.

 

[William Gaatjes]

I'll try to understand this later. Maybe.

I was acting like a dramaqueen. :biggrin:

But i am really enjoying vhdl.
Pretty soon i hope i have time again to restart my hobby project with my SAM7S as well. I have so much to do that i had to make decisions.
Pretty soon i hope to make a few more "I wonder" posts. After that, i will stick to electronics, software and computing.

To be honest, modelworks knows what i mean. ^_^.

 

[Cogman]

Good luck with it. I haven't had much experience with the XiLinks VHDL support. I've only dealt with its verilog support.

In my experience, xilinks had some pretty shitty support for verilog. I had problems where the solution was to start a new project and directly copy the source files from the non-working project to the new project.

Stuff like that sort of leaves a bad taste in my mouth over xilinks products.

 

[William Gaatjes]

Good luck with it. I haven't had much experience with the XiLinks VHDL support. I've only dealt with its verilog support.

In my experience, xilinks had some pretty shitty support for verilog. I had problems where the solution was to start a new project and directly copy the source files from the non-working project to the new project.

Stuff like that sort of leaves a bad taste in my mouth over xilinks products.

I will keep it in mind if i run into trouble that i cannot solve.
Thank you.
I have had not had any trouble so far.
The project i am doing is a more or less "simple" project. But it is fun to start with. It is an already existing project that needs to be upgraded. And that is where i come in. I reverse engineer the functionality and learn from it while i am making the desired improvements.

The more advanced projects at work use a lot bigger fpga to do all sorts of sine, cosine and fast fancy arithmetics to do real time processing on RF signals.
But that is something that i have not yet enough experience for to be assigned to and help out.

 

[William Gaatjes]

Well, cogman, i noticed something funny with the xilinx ide when using vhdl.
I am trying some examples to learn how to work with vhdl and understand the hierarchy of vhdl to be able to start from scratch.
The website fpga4fun has nice examples and is fun to read.

http://www.fpga4fun.com/index.html

And has some good pdf about vhdl and verilog. But i have only looked at the vhdl pdf files and assume it is the same for verilog as well.

This file seems to be a good pdf file to keep on the android phone or tablet or ipad/iphone.
http://ece.wpi.edu/~wrm/Courses/EE3810/geninfo/Welcome to the VHDL Language.pdf

The problem i experienced.
When describing an architecture , it must end with something as :

end PWM_arch;

(The example is below. )
I forgot to write this and i got no warning during synthesis.
And the build in code parser could not detect the error.
I use xilinx ide 13.3.
I did get a failure during implementation and the simulator does not work.
But i do find this odd that the parser was not able to detect it.



When looking at these coding examples :
I do have to note that i too would prefer verilog when given the chance.
It seems much more cleaned up.

Verilog :

module PWM(clk, PWM_in, PWM_out);
input clk;
input [7:0] PWM_in;
output PWM_out;

reg [8:0] PWM_accumulator;
always @(posedge clk) PWM_accumulator <= PWM_accumulator[7:0] + PWM_in;

assign PWM_out = PWM_accumulator[8];
endmodule

VHDL :

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity PWM is
  port (
   clk : in std_logic;
   PWM_in : in std_logic_vector (7 downto 0) := "00000000";
   PWM_out : out std_logic
  );
end PWM;

architecture PWM_arch of PWM is
  signal  PWM_Accumulator : std_logic_vector(8 downto 0);
begin
  process(clk, PWM_in)
  begin
    if rising_edge(clk) then      
      PWM_Accumulator  <=  ("0" & PWM_Accumulator(7 downto 0)) + ("0" & PWM_in);
    end if;
  end process;

  PWM_out <= PWM_Accumulator(8);
end PWM_arch;

 

[Borkil]

I just finished a class on vhdl and next fall will be taking another one and i really enjoyed it also!

when looking at these coding examples :
I do have to note that i too would prefer verilog when given the chance.
It seems much more cleaned up.

i really dont know anything about verilog but to me vhdl is a lot cleaner and easier to read albeit longer. The way that vhdl works is very hierarchical and reminds me some of OOP. The entity is a declaration of a block and tells what signals are inputs and outputs. The architecture of that entity says what the inside of the block will do. Very simple and straight forward to read!

What projects do you plan on doing William? What fpga are you using?

 

[esun]

I worked with VHDL a lot in my previous job (first targetting the Virtex-4, then the Virtex-6). It is extremely verbose, which has its goods and bads. It is very well structured because of its verbosity, and things tend to be uniform due to its strictness. However, there's a lot more typing than in Verilog.

Both are hierarchical in that you can create blocks of logic and integrate them into larger systems.

I've done a lot of VHDL for communication system emulation (e.g., digital up/down-conversion, FFTs, FEC decoders) in case you have any questions. VHDL is not particularly difficult really, system design is the hard thing. It's the same in the software world: learning a programming language is easy compared to learning how to architect large, complex programs.

 

[William Gaatjes]

I just finished a class on vhdl and next fall will be taking another one and i really enjoyed it also!



i really dont know anything about verilog but to me vhdl is a lot cleaner and easier to read albeit longer. The way that vhdl works is very hierarchical and reminds me some of OOP. The entity is a declaration of a block and tells what signals are inputs and outputs. The architecture of that entity says what the inside of the block will do. Very simple and straight forward to read!

What projects do you plan on doing William? What fpga are you using?

Well, work related projects i cannot mention with out approval.
It is not that secret or special, but we work for customers and is not a professional attitude to discuss work related projects.
Although i do can talk about some small sub circuits. As i did in highly technical. But that is just a very very small part and may not even be used. It is more my personal interest.

When it comes to hobby :
I hope to build a digital oscilloscope fast adc and logic analyzer for my self. Not very high in samplerate, but enough to be useful. When i get it working , i want to make it open source so other people can improve on it. It will have no screen or controls. But it will have wifi or some electrically isolated optic connection when wifi cannot be used. I was thinking that the pc, android phones or iphones are much better at displaying data and crunching numbers. But that is still far ahead. I am still very new and fresh at it.

Also, when i will create my little droid, i will need a fpga for sensor data gathering and processing and actuator control. And maybe a fpga to connect multiple arms together.

To be honest.
But that is maybe not necessary now 4core arm embedded chips start to arise. I think i am better off with embedded linux on some multi core chip with double camera inputs, gfx controller and dsp onboard. Linux has support for it anyway. Texas Instruments has some very powerful chips available.

Edit:
I forgot to mention that at the moment i am using one of the smaller chips, the spartanXC3s50A from Xilinx. It is not expensive and it is programmable without the use of expensive programming tools.
Yet it has a lot of features. The IDE webpack version from xilinx is free after registration. You will be granted a license file that is coupled with the hardware of your pc. The IDE is about 5 to 6GB in size.

 

[William Gaatjes]

I worked with VHDL a lot in my previous job (first targetting the Virtex-4, then the Virtex-6). It is extremely verbose, which has its goods and bads. It is very well structured because of its verbosity, and things tend to be uniform due to its strictness. However, there's a lot more typing than in Verilog.

Both are hierarchical in that you can create blocks of logic and integrate them into larger systems.

I've done a lot of VHDL for communication system emulation (e.g., digital up/down-conversion, FFTs, FEC decoders) in case you have any questions. VHDL is not particularly difficult really, system design is the hard thing. It's the same in the software world: learning a programming language is easy compared to learning how to architect large, complex programs.

Virtex chips are amazing. These chips are huge in size and capabilities.
If i have any questions, thank you. I will keep it in mind.
Perhaps because VHDL can do so much it seems a bit difficult. I have still the tendency to view logic as ports and flipflops. When i think of something i have to build, i see it as logic in my mind and that i translate into VHDL.
That is something i must partially let go off to become better at VHDL.
When optimizing it is far better to know how to manipulate VHDL to get the best logic design. But that requires knowledge of the innerworkings of the used fpga. And how the IDE translates the VHDL code into a working physical design.

 

[William Gaatjes]

Handy tip :

De xilinx chips have special clock modules called DCM.
It allows you to use it as a clock multiplier, a divider, or to create separate clocks with different phases such as 90 degrees, 180 degrees, 270 degrees.
Or just to create a delay for your clock.
Depending on the chip, you get more options such as multiple prescaler outputs or just more dcm blocks. 🙂

The xilinx IDE has a special wizard called core generator that allows you to customize the dcm to your needs. It will then generator for you the needed vhdl files.
You just have to add them and do the usual component description (just almost copy paste )and port mapping and you are ready to go.
The spartanXC3s50A has 2 DCM modules.
I just used 1 module to generate a divide by 6 divider.
I have a 32MHz input. I needed a ~5MHz output. Now i have a 5.333MHz clock. ^_^
It saves on used logic blocks using these DCM blocks.

For a short spartan3a family description :
http://www.xilinx.com/support/documentation/data_sheets/ds706.pdf

User guides :
http://www.xilinx.com/support/documentation/spartan-3a_user_guides.htm

 

[esun]

As a general note, if you want to do anything common but non-trivial to implement, look for an IP core before implementing it yourself. E.g., clock generators, DDFS, fast adders and multipliers, memory elements (FIFOs, shift registers, RAMs), CORDIC, and more all have IP cores you can generate use coregen (not sure how many are free).

You can also get cores at www.opencores.org.

 

[degibson]

... I have still the tendency to view logic as ports and flipflops. When i think of something i have to build, i see it as logic in my mind and that i translate into VHDL.
That is something i must partially let go off to become better at VHDL. ...

Don't let it go -- just do more of it.

 

[sm625]

I hope you're still enjoying it when you have to have 8 different versions of Xilinx software installed and all 8 versions produce mcs files that behave differently inside the fpga...

 

[William Gaatjes]

I hope you're still enjoying it when you have to have 8 different versions of Xilinx software installed and all 8 versions produce mcs files that behave differently inside the fpga...

To be honest, at my work i was warned in advance by people with experience in VHDL and Xilinx to not just update if there is no need to. At the moment everything seems to work for me how i had it thought up. But as mentioned before, i am hardly pushing the VHDL IDE to its limits.

Don't let it go -- just do more of it.

I am finding a balance in it. First it is good to see if it can be simplified into simple logic. For example when doing arithmetic. When it is of no use, i abandon the view as logic approach and see a black box with inputs, outputs and functionality that must be programmed. If i am lucky, there is something that can be simplified again. I do like to know how the code is mapped into the logicblocks and how the translation and mapping of the IDE operate.
Having that kind of knowledge makes debugging easier. Especially if it is known how the target device operates internally.

 

[William Gaatjes]

As a general note, if you want to do anything common but non-trivial to implement, look for an IP core before implementing it yourself. E.g., clock generators, DDFS, fast adders and multipliers, memory elements (FIFOs, shift registers, RAMs), CORDIC, and more all have IP cores you can generate use coregen (not sure how many are free).

You can also get cores at www.opencores.org.

Thank you for this site, i am enjoying it.