The .13u fabrication process has been problematic for all companies that have transitioned to it. Intel was the first to make the jump successfully, but it did not disclose the cost nor trouble that it encountered in the conversion. Intel has millions and millions to invest in fabrication techniques and technology, and it used a total of 4 Fabs to transition to the .13u process, with each one doing it its own way instead of the copy exact technique Intel was famous for. This hints that the problems with the .13u process were so severe, that Intel was willing to use 4 of its mega-Fabs to test and troubleshoot the process, each in its own separate way. Every lesson learned from each Fab eventually made its way into the other Fabs. This is like using 4 separate minds to work on a problems from many angles, with each conferring with the other on what they have learned. Most semi-conductor companies do not have this luxury. AMD, Infineon, UMC, TSMC, and others had to do this piecemeal and figure out the problems one step at a time (as Intel is not going to help them out). Only now are we starting to see .13u parts from AMD, fully 9 months from when Intel released its .13u Pentium 4 part. Other companies like TSMC and UMC are only now getting their .13u lines up to mass production.
One of the main problems with the new process was that perfectly good dies would fail around 300 hours of use. This perplexed engineers all over the world, as this should not have been happening. This failure was seen time and time again, and eventually yields would eventually reach around 10% after testing. The main culprit in this case turned out to be voids in the copper that under heat and pressure would migrate to the interconnects. Once the void reaches the interconnect, it would essentially dislodge the transistor, causing large portions of the chip to fail. There was no simple way around this problem, and in the end the .13u design libraries had to be changed to reflect this. The change in the design libraries seems to have helped this problem and yields on the .13u process are now becoming acceptable. The problem with changing the design libraries is that chips designed around the old libraries had to be re-designed to reflect the new libraries.
This looks to be where the delay in the NV-30 stems from. TSMC had to change its design libraries for the .13u process, and in so doing has forced NVIDIA (and other companies) to redesign their chips to work on the process. This is especially painful for the NV-30, as it comprises nearly 130 million transistors. The redesign on such a part using the new libraries is a huge task. New simulations must be made, new testing, and new troubleshooting. While not exactly starting from scratch, it is much like deciding to add a second story to a new one story house. The foundation and first floor can remain intact, but a lot of extra work is required to get the building up and inhabitable.
Relying on the latest fabrication technology is a risky venture, but one that has paid off for NVIDIA time and again. Eventually their luck would run out, and the .13u process seems to have offered the opportunity for bad luck to come and visit. NVIDIA may or may not be part of the blame here, but the fact remains that NVIDIA is well behind schedule and this has allowed the competition to catch up and release compelling products at both the high end and mainstream. Transitioning to the .13u process will eventually bear fruit, and NVIDIA is well ahead of the curve in terms of utilizing this process for products from the top to bottom. This will eventually pay off, and their expertise in working with .13u products will be second to none. When future NV-30 variants start to get close to production, the experience NVIDIA has gained here will pay off in spades. The transition to these future products will most likely be a lot smoother, and the late spring introduction of DX9 mainstream parts will most certainly help NVIDIA to keep pressure on the industry.
