A
Translation lookaside buffer (TLB) is a memory
cache that is used to reduce the time taken to access a user memory location.
[1][2] It is a part of the chip’s
memory-management unit (MMU). The TLB stores the recent translations of
virtual memory to
physical memory and can be called an address-translation cache. A TLB may reside between the
CPU and the
CPU cache, between CPU cache and the main memory or between the different levels of the multi-level cache. The majority of desktop, laptop, and server processors include one or more TLBs in the memory management hardware, and it is nearly always present in any processor that utilizes
paged or
segmented virtual memory.
The TLB is sometimes implemented as
content-addressable memory (CAM). The CAM search key is the virtual address and the search result is a
physical address. If the requested address is present in the TLB, the CAM search yields a match quickly and the retrieved physical address can be used to access memory. This is called a TLB hit. If the requested address is not in the TLB, it is a miss, and the translation proceeds by looking up the
page table in a process called a
page walk. The page walk is time consuming when compared to the processor speed, as it involves reading the contents of multiple memory locations and using them to compute the physical address. After the physical address is determined by the page walk, the virtual address to physical address mapping is entered into the TLB. The
PowerPC 604, for example, has a two-way
set-associative TLB for data loads and stores.
[3] Some processors have different instruction and data address TLBs.
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