Originally posted by: imgod2u
Wow, I hope the Sandra SSE2 benchmarks aren't correctly showing what the final silicon will be able to do because the P4 wrecks the Athlon64 in the floating point SSE2 ops (though the Athlon64 is within striking distance on the integer SSE2 ops). Otherwise the scores are good, but nothing like what AMD built us up to believe it would be like. Judging by AMD's earlier comments I thought the Athlon64 would thoroughly massacre the P4 in everything from the get go.
Well, the SSE2 performance is understandable. While Intel skimped quite a bit on x87 support and many integer-intensive tasks are very branch-heavy (hence, the hyperpipelined design would hold it back), SSE/SSE2 performance on the P4, even on a clock-normalized scale, was focused on quite a bit. The K8 has the same SSE/SSE2 execution resources as the P4 does and since the data-to-instruction ratio is very high in such operations, the P4's limited scheduling and issuing bottlenecks aren't a concern. It's mostly data-limited and the P4's caching and memory subsystem should be quite sufficient at supplying the data neccessary for SSE/SSE2 operations.
I'd be curious to see how many benchmarks are seriously effected by the use of a 1 MB L2 cache as Prescott will be evening that playing field very shortly after the Athlon64's launch. Also, judging by the Athlon64's performance in 3DS Studio and Lightwave AMD engineers still have to work heavily on that SSE2 unit to bring it up to par with Intel's. The Opteron's memory latency on the other hand is exceptional, too bad AMD is choking the chip with single channel DDR though.
The SSE2 unit, by all means, are on par with the P4's. The difference is, the P4 has a significantly higher clockrate. You can't really do much more than 1 SSE2 instruction per clock, the parallel execution resources neccessary would be tremendous and more than anything available of any x86 processor I've ever seen.
The point though, isn't whether or not they are on par with the P4s on a clock-normalized basis. Hammer has to be equal to the P4-even with a huge clock disadvantage as the P4 will likely always be waaaay ahead of the Hammer in terms of pure frequency. Without that, the P4 will be wiping the floor with the Hammer on an increasing number of SSE2-optimized programs. This is especially bad for AMD in that since both companies will now have SSE2 units, software makers will be seeing the instruction set as standard and include it into more and more programs.
All in all I hope that they can significantly tweak this CPU before it's released because otherwise Prescott will be very bad news for AMD. I'm a little disappointed in the benches as I expected AMD to clearly be ahead of the P4 in almost all tasks.
Well, expectations lead to disappointment because your expectations are almost always going to be unreasonably high. I think the chip did pretty well for a 1.6 GHz part that's suppose to be scalable up to 2.4 GHz and beyond.
I really hope you're right, but judging by the fact that it's a year late and this is only running at 1.6 GHz it may be a tad optimistic. Also, the fact that this is a 1.6 GHz part and the numbers in these benchies show me that AMD's "we're waiting for 64-bit Windows" excuse is not the only reason they're waiting 'till Sept. to launch
OT: Does anyone else see how this shows that AMD's model number scheme is fundamentally flawed? (despite the fact that they claim it is a Tbird comparison)
A lot of people did and still do to this day. There have been many a threads about it. But there will always be fanboys eating out of the hands of marketing of their favorite pet company.
