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Question x86 and ARM architectures comparison thread.

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never implied that I only meant that cheating in GB with cluster level hacks is something I dislike.
Do you think SME was created for cheating in Geekbench?

Apple has had matrix mul accelerators since the A13. But it was never exposed to devs until SME was standardised by ARM.
 
Do you think SME was created for cheating in Geekbench?

Apple has had matrix mul accelerators since the A13. But it was never exposed to devs until SME was standardised by ARM.
No it had real use cases in matmul but it's at best is getting used in GB6 ST benchmark to look good it's inflating score by 5-6% i am yet to see a public sw take advantage of this
 
Do you think SME was created for cheating in Geekbench?
It's the other way around. It's not the hardware that's cheating but Geekbench that's becoming progressively worse over time.

In Geekbench 4 the public version had easy sorting options, the Integer ST, Integer MT, FP ST and FP MT were separated along with memory score. Now you have to sort through their PDF to determine what is Int and what is FP and look at their arbitrary scoring schemes to get the score. I'm not sure you can even sort on Geekbench 6. In GB5 you could sort by adding commands to the URL. It's becoming more closed source and proprietary mirroring the Smartphone ecosystem.
 
In Geekbench 4 the public version had easy sorting options, the Integer ST, Integer MT, FP ST and FP MT were separated along with memory score. Now you have to sort through their PDF to determine what is Int and what is FP and look at their arbitrary scoring schemes to get the score. I'm not sure you can even sort on Geekbench 6. In GB5 you could sort by adding commands to the URL. It's becoming more closed source and proprietary mirroring the Smartphone ecosystem.
What you rightly complain about is not a property of the application but of Primate Labs site.
 
In GB6, I don’t think it can be sorted, certainly not like before as was said. @DavidC1 have you tried using the same sort commands as in GB5 for GB6?

Side note, I have a python script that iterates over each page and grabs the headline numbers. Not ideal for getting granular data but it’s something.
 
1763075493545.png
The current landscape for P cores
* Cores are counted without L2 logic + sram arrays + tags. LNC specifically has the L0+L1, but not L2. Could be considered an area underestimate.
** Based on multiplying out the 9950x score by the ratio of Fmax of Turin Dense divided by the 9950x Fmax. Should be considered a large underestimate, maybe a worst case scenario.

x86 cores have wider vector width, making their FPUs relatively larger, esp for Zen 5C which has AVX-512.
 
In GB6, I don’t think it can be sorted, certainly not like before as was said. @DavidC1 have you tried using the same sort commands as in GB5 for GB6?
I think I have, and it didn't work. The way they don't separate out Int and FP makes me think they don't even understand what they are creating. Going in the direction of uselessness as free Android performance tests.
 
I think I have, and it didn't work. The way they don't separate out Int and FP makes me think they don't even understand what they are creating. Going in the direction of uselessness as free Android performance tests.
funnily thry do separate out int and FP scores but only on the ios and android app

the website however doesn't display this

IMG_2946.pngIMG_2945.png
 
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I think I have, and it didn't work. The way they don't separate out Int and FP makes me think they don't even understand what they are creating. Going in the direction of uselessness as free Android performance tests.
They do, they're just not showing it in the browser anymore.
Geomean of INT subtests has a 65% weight in the total score.

** Based on multiplying out the 9950x score by the ratio of Fmax of Turin Dense divided by the 9950x Fmax. Should be considered a large underestimate, maybe a worst case scenario.
Can't really do that, as clock speed drops, your PPC increases.
Anyway, there's no need to guess about the score since it's searchable in the browser (all 2 of them lol).
edit: there's another bare-metal entry for 9645

At this point though gb5 1t is just as questionable as gb6. The compiler versions are very dated; not only that, they're also different depending on the OS, unlike gb6.
1763085145862.png
 
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Can't really do that, as clock speed drops, your PPC increases.
true, hence why I think it's a large underestimate. That, and DC parts clock a good bit lower than DT parts.
Anyway, there's no need to guess about the score since it's searchable in the browser (all 2 of them lol).
Thanks, I didn't know the ability to search for GB5 scores still existed lol. How can one do that?
At this point though gb5 1t is just as questionable as gb6. The compiler versions are very dated; not only that, they're also different depending on the OS, unlike gb6.
TBF it's still much more standardized than spec2017, hence the GK android phone score fiasco regarding spec2017, and also a benchmark that has a nice range of workloads , which makes it very useful for generalized performance- unlike cinebench.
It also doesn't get impacted by AMX as much, which makes it nice to look at *just the core*.
 
No it had real use cases in matmul but it's at best is getting used in GB6 ST benchmark to look good it's inflating score by 5-6% i am yet to see a public sw take advantage of this

executorch and ONNX use SME2 by default
 
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executorch and ONNX use SME2 by default
Not to mention everything in MacOS/iOS that was using AMX for all those years that is now using SME.

I don't understand why there is such widespread acceptance of AVX including in benchmarks but SME, which is addressing a lot of the same use cases is unacceptable. Nobody thinks Apple is using SME in FCP/Logic? Really? FFS, Blender supports SME, a lot of the linear solvers/frameworks in data science already support it. There's probably thousands of python projects out there already using it without realizing.
 
Not to mention everything in MacOS/iOS that was using AMX for all those years that is now using SME.

I don't understand why there is such widespread acceptance of AVX including in benchmarks but SME, which is addressing a lot of the same use cases is unacceptable. Nobody thinks Apple is using SME in FCP/Logic? Really? FFS, Blender supports SME, a lot of the linear solvers/frameworks in data science already support it. There's probably thousands of python projects out there already using it without realizing.
The problem for me is not Sme But SME being part of ST performance when it's not part of a single Core..
 
No it had real use cases in matmul but it's at best is getting used in GB6 ST benchmark to look good it's inflating score by 5-6% i am yet to see a public sw take advantage of this
Any software that used Accelerate framework could take advantage of AMX. Now, any software written with SME instructions.

AMX was always intended to be used via CPU instructions but Apple had to wait for Arm to add support for it.

The fact of the matter is that Apple waited on SVE to be matured to fully make the jump to adopting it, and AMX was simply a stopgap solution to address the shortcomings of Arm NEON.

 
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Not to mention everything in MacOS/iOS that was using AMX for all those years that is now using SME.

I don't understand why there is such widespread acceptance of AVX including in benchmarks but SME, which is addressing a lot of the same use cases is unacceptable. Nobody thinks Apple is using SME in FCP/Logic? Really? FFS, Blender supports SME, a lot of the linear solvers/frameworks in data science already support it. There's probably thousands of python projects out there already using it without realizing.
It is because AVX512 was the last bastion of performance superiority for x86 (AMD).

People who complain about SME boosting M4's ST never complain about Zen4 AVX512 boosting Object Detection by even more.
 
The problem for me is not Sme But SME being part of ST performance when it's not part of a single Core..
What's the problem if it's a CPU instruction set?

Are users who are benefiting from SME complaining that their software is running faster but the boost didn't come from transistors inside the P core?
 
What's the problem if it's a CPU instruction set?

Are users who are benefiting from SME complaining that their software is running faster but the boost didn't come from transistors inside the P core?
like i have said i don't have any problem with it being part of the core but it's not part of the core like AVX-512/NEON/SVE AARE
 
Can you tell us what the problem is for developers and users, if any?
The problem for me is that it's skewing Geekbench average for a category which it is not part of imo I don't have any issue with it's existence.
 
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