Would it be possible to make the cells of memory that want to be "on" rather than "off"?

[MadRat]

Seems to me that memory is a large waste of electricity because its always being pumped full of current to keep it refreshed that eventually bleeds off into the surroundings. Would it be possible to reverse this and make the electrons in the surrounding material try to leach into each cell therefore requiring memory cells be bled to induce an "on" (empty of electrons) state.

 

[Geniere]

Yes it's possible, but presently its a question of real estate. Other types of memory would reguire more componants making a memory chip bigger, more expensive and slower.

Regards

 

[pm]

It sounds like you are referring to DRAM (as opposed to SRAM). In DRAM the charge is held by a capacitor which needs to be refreshed to maintain charge on the capacitor. In transistors, the majority carriers are either electrons or "holes" which are charge carriers that are the absence of electrons. DRAM uses NMOS transistors as the device that locks the charge in the cell and then opens for reading and writing. Using current silicon technology, switching the device from an NMOS (electron majority carrier) to a PMOS (hole majority carrier) would would be a net loss in either density or speed. PMOS devices take up more space for a given amount of current drive strength compared to an NMOS device which would result in either large DRAM cells, or similarly sized slower DRAM cells.

But I imagine that you are actually referring to the capacitor. Switching the capacitor over would result in no net gain at all. Currently charge leaks out of the cell, if you switched it the other way, charge would end up leaking in. In either case charge carriers are attempting to move towards a steady state and whether the value of the cell is held by a 0V signal or a 1.8V/3V/5V signal wouldn't matter since you'd still need to do refreshes.

Since the charge is being held by a leaky capacitor and a leaky NMOS device no matter what you do if you want DRAM you need refreshes. To reduce the frequency of the refresh cycles you could increase the capacitance of the capacitor by changing the material properties or the increasing dimensions of the capacitor or decreasing the material separation, or you could reduce the leakiness of the materials - which would slow them down - or you could improve the ability of the cell readers (sense amplifiers) to discern ones and zeros.

 

[MadRat]

So you actually want the quick leakage is what you are saying?

 

[MadRat]

I should mention the reason I bring this up. I'm guessing that a fuel-consuming memory technology could be developed. The charge of the matrix would attract fresh fuel to the surface whereas the same fuel would be repelled once spent. The cell would be an organic (not living tissue per se, just organic) molecule that could have multiple states depending on which pathways stimulates it. Pathways could be done within several levels, allowing multiple ports per memory cell. A membrane over the entire surface of the memory device would allow the recharging of the fuel and allow byproducts to be released, like how cells aspire waste. Switching between states would be near instantaneous. Signals speed would still be the limiting factor still, but hopefully such an idea would eliminate the need for a refresh.

It may sound like a far fetched idea, but one should never discard ideas become they simply sound inefficient. Besides that, fuels aren't always hydrocarbons and can be very simple chemical structures where the difference between spent and fresh is a simple swap of a molecule...

 

[CTho9305]

Originally posted by: pm
It sounds like you are referring to DRAM (as opposed to SRAM). In DRAM the charge is held by a capacitor which needs to be refreshed to maintain charge on the capacitor. In transistors, the majority carriers are either electrons or "holes" which are charge carriers that are the absence of electrons. DRAM uses NMOS transistors as the device that locks the charge in the cell and then opens for reading and writing. Using current silicon technology, switching the device from an NMOS (electron majority carrier) to a PMOS (hole majority carrier) would would be a net loss in either density or speed. PMOS devices take up more space for a given amount of current drive strength compared to an NMOS device which would result in either large DRAM cells, or similarly sized slower DRAM cells.

But I imagine that you are actually referring to the capacitor. Switching the capacitor over would result in no net gain at all. Currently charge leaks out of the cell, if you switched it the other way, charge would end up leaking in. In either case charge carriers are attempting to move towards a steady state and whether the value of the cell is held by a 0V signal or a 1.8V/3V/5V signal wouldn't matter since you'd still need to do refreshes.

Since the charge is being held by a leaky capacitor and a leaky NMOS device no matter what you do if you want DRAM you need refreshes. To reduce the frequency of the refresh cycles you could increase the capacitance of the capacitor by changing the material properties or the increasing dimensions of the capacitor or decreasing the material separation, or you could reduce the leakiness of the materials - which would slow them down - or you could improve the ability of the cell readers (sense amplifiers) to discern ones and zeros.

Want to also explain why my "leak to the middle" idea isn't used?

 

[SuperTool]

If cells would "want" to be "on" then eventually the 0 values would become 1 unless you refreshed them by leaking off positive charge.
So you would still have to refresh and burn power.
It doesn' t matter if positive charge leaks into the cell and then you discharge it, or if you put positive charge into the cell and then it leaks out. Still you need to refresh, and positive charge moves from + to - eventually, so you use power.

 

[f95toli]

Stupid question: Why not simply but NOT-gates on all the data-lines from the memory? This would do the trick.
The only problem is that now you need to refresh the memory in order to keep the zeros (ones in the memory module) so you would not gain anything.

 

[MadRat]

Molecular gates would not need a refresh. They would need something to slant them to a homeostasis in the event of a "clear" state signal.

 

[Era]

Molecules do consume or relieve energy every time they change their state.
There is no perpetual machine there. IMHO.

 

[MadRat]

And whats your point?

Ever see how muscles work on the microscopic level? Nerves? Molecules are very efficient at holding a state for prolonged periods of time.

 

[Era]

My point is that electro-chemical or biolgical systems react very slow compared to a system of transistors.
The power of our brains, for example, is of it's remarkable parallelsmim, not the speed of the neurons.

A molecule can hold it's state indefenitely, but changing it's state takes "forever" compared to transistors.

That was my point.

 

[Mday]

i think pm means that it'd be more expensive to make, and highly inefficient if you want to save power in that manner.

 

[Era]

No, I don't mean that it would be too expensive. It's just that nobody knows how to make memory out of molecules. If someone would know (or will), it would be quite cheap to produce(I think).
A fly's brain can hold quite amount of data, and even processing power, and it would take only sugar and some sh|t.

But, molecules, compared to transistors, are really slow. So, molecular memory structure would have to be very different then the transistor memory. It would have to have more parallesmism(and I don't mean data bus) and a different kind of logic to control it, like a processor(s).

Well, this is just ranting, please don't mind.