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Will having 4 sticks of RDRAM decrease OCing potential as opposed to 2 sticks??!?!
- Thread starter x86
- Start date
DivideBYZero
Lifer
I belive that the latency increases when you increase module count. This is due to the fact that RDRAM is on a serial connection, shared between all the modules. DDR RAM is Parrallel(sic?), hence module count does not impact latency.
Not sure that this would affect your FSB limit, but benchmark figures will probably drop.
Someone let me know if I'm wrong.
Not sure that this would affect your FSB limit, but benchmark figures will probably drop.
Someone let me know if I'm wrong.
DivideBYZero
Lifer
Chill out baldy!!
The guy is asking for extra info, not attacking your intelect!
x86: Get all the info you can on the matter before you buy. This is your machine, not Baldies!
The guy is asking for extra info, not attacking your intelect!
x86: Get all the info you can on the matter before you buy. This is your machine, not Baldies!
If you think of it probability wise, more ram modules will have a higher rate of failure than fewer ram modules, even if success rate is incredibly high per module.
This is due to the fact that RDRAM is on a serial connection, shared between all the modules. DDR RAM is Parrallel(sic?), hence module count does not impact latency.
And i'm pretty sure that since Rdram is on a serial connection, more modules will NOT impact latency. if you have 4 RIMMS, all the rimms are connected when you operate at any given time (hence the need for c-rimms if you plan to leave a bank empty).
As for DDR SDram, I have no clue how they operate.
This is due to the fact that RDRAM is on a serial connection, shared between all the modules. DDR RAM is Parrallel(sic?), hence module count does not impact latency.
And i'm pretty sure that since Rdram is on a serial connection, more modules will NOT impact latency. if you have 4 RIMMS, all the rimms are connected when you operate at any given time (hence the need for c-rimms if you plan to leave a bank empty).
As for DDR SDram, I have no clue how they operate.
DivideBYZero
Lifer
Check this about the latency increase afforded by extra RIMM's, it seems I am a God after all...
http://www.hardwarecentral.com/hardwarecentral/reviews/1647/3/
<< Similarly to a series electrical circuit, versus a parallel circuit, the data being requested from an RDRAM RIMM must pass through each and every one of a RIMM's chips. Likewise, when a second RIMM is added, the signal must pass not only through the first RIMM, but through each chip on the second RIMM as well. The more chips the signal must pass through the longer it will take to reach its destination. Furthermore, while initially this doesn?t appear too large an issue, it is important to remember that the second RIMM will almost always carry a much greater latency than the first, due to a number of electrical factors and the greater physical distance from the Memory Controller Hub. >>
http://www.hardwarecentral.com/hardwarecentral/reviews/1647/3/
<< Similarly to a series electrical circuit, versus a parallel circuit, the data being requested from an RDRAM RIMM must pass through each and every one of a RIMM's chips. Likewise, when a second RIMM is added, the signal must pass not only through the first RIMM, but through each chip on the second RIMM as well. The more chips the signal must pass through the longer it will take to reach its destination. Furthermore, while initially this doesn?t appear too large an issue, it is important to remember that the second RIMM will almost always carry a much greater latency than the first, due to a number of electrical factors and the greater physical distance from the Memory Controller Hub. >>
I believe that this article is dated. It still carries pertenance to i820 RDram (single channel) not i850 RDram (Dual channel). They say that 820 is NOT a good example of an RDram chipset.
The bottom line is this: i820 is NOT a good chipset. In fact, i820 is likely hampering RDRAM?s performance. Basing our analysis of RDRAM performance on benchmarks obtained using the i820 chipset would be like judging SDRAM performance from benchmarks obtained with a VIA Apollo Pro Plus board, for example.
Even on the i840 (Dual channel) which i850 was derived from, it says...
Instead, a better representation of RDRAM performance would test it on the i840 chipset, with its dual RDRAM channels, operating in lock-step. At best, that translates into over 3200 MB/s of bandwidth using PC800 memory, and at worst, using PC600, 2066 MB/s, still twice as much as PC133 SDRAM. Furthermore, the dual RDRAM channels can actually serve to slightly lower memory latency, a very important factor.
In fact the i820 didnt even require c-rimm terminators, it wasnt truly serial, only the occupied RIMM banks were in serial, and yes if you add one in you are lengthing the serial connection.
The bottom line is this: i820 is NOT a good chipset. In fact, i820 is likely hampering RDRAM?s performance. Basing our analysis of RDRAM performance on benchmarks obtained using the i820 chipset would be like judging SDRAM performance from benchmarks obtained with a VIA Apollo Pro Plus board, for example.
Even on the i840 (Dual channel) which i850 was derived from, it says...
Instead, a better representation of RDRAM performance would test it on the i840 chipset, with its dual RDRAM channels, operating in lock-step. At best, that translates into over 3200 MB/s of bandwidth using PC800 memory, and at worst, using PC600, 2066 MB/s, still twice as much as PC133 SDRAM. Furthermore, the dual RDRAM channels can actually serve to slightly lower memory latency, a very important factor.
In fact the i820 didnt even require c-rimm terminators, it wasnt truly serial, only the occupied RIMM banks were in serial, and yes if you add one in you are lengthing the serial connection.
Nope. RDRAM is an entirely serial system. Each additional device on the bus, and therefore each additional RIMM, adds to the latency.
All RDRAM based systems require CRIMM terminators in empty slots.
The i820 chipset requires CRIMMs in empty slots. It simply did not require RDRAM to be in pairs.
DivideBYZero has been correct all the way through.
All RDRAM based systems require CRIMM terminators in empty slots.
The i820 chipset requires CRIMMs in empty slots. It simply did not require RDRAM to be in pairs.
DivideBYZero has been correct all the way through.
x86, do I have to spoonfeed you every time? I know you don't want to make a big mistake like you did last time, but please, do a little reading.
More latency means slower performance. Less latency means faster performance.
Additional RIMMs will reduce your potential to overclock as you have to come up against the limitations for more devices. The chances of 2 RIMMs doing well is much higher than 4 RIMMs doing well.
Look at it mathematically. For example, a RIMM has an 80% chance of getting to PC1066 levels. With 2 RIMMs, this is 0.8 x 0.8, which gives you a 64% chance of getting to PC1066. With 4 RIMMs, it becomes 0.8 x 0.8 x 0.8 x 0.8, or 41%.
More latency means slower performance. Less latency means faster performance.
Additional RIMMs will reduce your potential to overclock as you have to come up against the limitations for more devices. The chances of 2 RIMMs doing well is much higher than 4 RIMMs doing well.
Look at it mathematically. For example, a RIMM has an 80% chance of getting to PC1066 levels. With 2 RIMMs, this is 0.8 x 0.8, which gives you a 64% chance of getting to PC1066. With 4 RIMMs, it becomes 0.8 x 0.8 x 0.8 x 0.8, or 41%.
Andy is correct about the probability decreasing as the number of devices going up. But I have a related question. If you have RAM sticks which are tested stable at high speeds, say PC1066 speeds individually( or in pairs as applied to 850 chipset), then will they overclock to the same speed if all 4 are used simultaneusly?
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