Why would I need a 2T command rate after upgrade to X2?

[RadiclDreamer]

Originally posted by: akshayt
Isn't 2T to 1T big difference?

Depends on what you cal big, in my experience its been 1-3% which dont consider much

 

[CaiNaM]

Originally posted by: akshayt
Isn't 2T to 1T big difference?

does making a ram divider make a difference?

this has been discussed to death, but no noticeable difference, altho in certain benchmarks you may see a few % pts in favor of 1t timings (1.1 - 2.1% or 30mb/s)... in fact, if 2t allows you a greater overclock, it can even make up the difference and then some. it's of little significance with a64's architecture (on-die memory controller).

forget cas latency, ram dividers, etc: cpu MHz is still king - within the same architecture, of course .

testing my xms512-3200c2pro some time ago, i reached the same conclusion as countless others as the difference in memory bandwidth between cas2 and cas3 latency was basically non-existent (within a reasonable margin of error of less the 1%, or 3-4mb/s). realworld tests doing video encoding, file compression/decompression, and gaming showed no measurable difference either.

running the same "real world" applications @ 5/4 divider or 1t/2t again only showed differences within a similar margin of error - differences which were more than compensated for by the higher overclocks avail by running "looser" memory timings.

not that there's anything wrong with being anal about a 1-2% difference in a particular benchmark. there is certainly nothing wrong with trying to squeeze out a couple of extra % pts if you're trying to make the benchmark hall of fame (i mean, how much faster is a pc that gets 5000 on 3dm06 compared to one that gets 4950?), as long as it's not creating a greater disadvantage in another area (like CPU or ram MHz, or having to run fewer sticks of ram - 1gb instead of 2gb for example).

 

[5t3v0]

Well, finally I have prime stability (11 hours) at 2.5GHz (11x227) but had to go to +0.15v on the vcore which is fluctuating in the region of 1.57v to 1.61v at idle and 1.55v to 1.57v under load. I've enabled CnQ to bring this down to 1.1GHz with 1.35v - 1.37v for light use. Might try lower vcore with RMClock.

Max load temp under prime95 was 64C which is higher than I would like but then if Mucker is right, the readings for vcore and temp are not to be trusted on these Epox boards. Saying that, my Opty hardly ever reached mid 50sC on the same board so I'd still like to lower this & may reseat the HSF with some better thermal grease. I'm currently using Arctic Alumina but may get AS5 instead. I have a tube of AC MX-1 - anyone know what this is like?

Still having to use 2T which is a (small) sacrifice I'm going to have to make by the looks of it. I still dont understand why 2T should be necesary at stock settings though. I sent a request to Epox support who just sent me back the AMD supported memory list. Helpful! Its also sitting with AMD support. Might try G.Skill too.

There are 2 new memory options with the latest BIOS - "DRAM Bank Interleaving" which is defaulted to "Enable", and "Burst length" which is defaulted to "4 beats". Anyone know if I should change any of these?

Thanks for the posts.

Steve

 

[CaiNaM]

Originally posted by: 5t3v0
There are 2 new memory options with the latest BIOS - "DRAM Bank Interleaving" which is defaulted to "Enable", and "Burst length" which is defaulted to "4 beats". Anyone know if I should change any of these?

Thanks for the posts.

Steve

from: http://www.adriansrojakpot.com/Speed_Demonz/BIOS_Guide/BIOS_Guide_Index.htm

SDRAM Bank Interleave

Options : 2-Bank, 4-Bank, Disabled

This feature enables you to set the interleave mode of the SDRAM interface. Interleaving allows banks of SDRAM to alternate their refresh and access cycles. One bank will undergo its refresh cycle while another is being accessed. This improves performance of the SDRAM by masking the refresh time of each bank. A closer examination of interleaving will reveal that since the refresh cycles of all the SDRAM banks are staggered, this produces a kind of pipelining effect.

If there are 4 banks in the system, the CPU can ideally send one data request to each of the SDRAM banks in consecutive clock cycles. This means in the first clock cycle, the CPU will send an address to Bank 0 and then send the next address to Bank 1 in the second clock cycle before sending the third and fourth addresses to Banks 2 and 3 in the third and fourth clock cycles respectively. The sequence would be something like this :-

1. CPU sends address #0 to Bank 0
2. CPU sends address #1 to Bank 1 and receives data #0 from Bank 0
3. CPU sends address #2 to Bank 2 and receives data #1 from Bank 1
4. CPU sends address #3 to Bank 3 and receives data #2 from Bank 2
5. CPU receives data #3 from Bank 3

As a result, the data from all four requests will arrive consecutively from the SDRAM without any delay in between. But if interleaving was not enabled, the same 4-address transaction would be roughly like this :-

1. SDRAM refreshes
2. CPU sends address #0 to SDRAM
3. CPU receives data #0 from SDRAM
4. SDRAM refreshes
5. CPU sends address #1 to SDRAM
6. CPU receives data #1 from SDRAM
7. SDRAM refreshes
8. CPU sends address #2 to SDRAM
9. CPU receives data #2 from SDRAM
10. SDRAM refreshes
11. CPU sends address #3 to SDRAM
12. CPU receives data #3 from SDRAM

As you can see, with interleaving, the first bank starts transferring data to the CPU in the same cycle that the second bank receives an address from the CPU. Without interleaving, the CPU would send the address to the SDRAM, receive the data requested and then wait for the SDRAM to refresh before initiating the second data transaction. That wastes a lot of clock cycles. That's why the SDRAM's bandwidth increases with interleaving enabled.

However, bank interleaving only works if the addresses requested consecutively are not in the same bank. If they are, then the data transactions behave as if the banks were not interleaved. The CPU will have to wait till the first data transaction clears and that SDRAM bank refreshes before it can send another address to that bank.

Each SDRAM DIMM consists of either 2 banks or 4 banks. 2-bank SDRAM DIMMs use 16Mbit SDRAM chips and are usually 32MB or less in size. 4-bank SDRAM DIMMs, on the other hand, usually use 64Mbit SDRAM chips though the SDRAM density may be up to 256Mbit per chip. All SDRAM DIMMs of at least 64MB in size or greater are 4-banked in nature.

If you are using a single 2-bank SDRAM DIMM, set this feature to 2-Bank. But if you are using two 2-bank SDRAM DIMMs, you can use the 4-Bank option as well. With 4-bank SDRAM DIMMs, you can use either interleave options.

Naturally, 4-bank interleave is better than 2-bank interleave so if possible, set it to 4-Bank. Use 2-Bank only if you are using a single 2-bank SDRAM DIMM. Note, however, that Award (now part of Phoenix Technologies) recommends that SDRAM bank interleaving be disabled if 16Mbit SDRAM DIMMs are used. This is because early 16Mbit SDRAM DIMMs used to have stability problems with bank interleaving. All SDRAM modules can now use bank interleaving without stability problems.

So essentially -

Bank Interleave:
Set to "4-Way". Set to "2-Way" if u have 2-bank RAM stick.

SDRAM Burst Length:
Set to 8 for longer burst length and better performance. Revert back to 4 if system becomes unstable.

 

[5t3v0]

On the Epox is "Enable" or "Disable". Who knows if Enable is 2 way or 4 way. Perhaps it works it out for you based on the ram installed.

 

[5t3v0]

Originally posted by: Mucker
I settled on 1.60v for Epox (+0.20). 1.525 on the DFI....

What temps are you getting on the Epox with that vcore?

I ran USDM and Core Temp side by side with 2 prime95 sessions. USDM was reading 63C while CT was reading 54C (+-2) on one core and 57C (+-2) on the other core. Interestingly CT was reading about 5C higher than USDM when prime95 had just started up. How can you trust one app to be any more accurate than another? I am using AS Ceramique but have ordered some AS5 to replace it. Hopefully will get the max temp to under 60C.

Still not happy about the 2T CPC. Shouldnt happen with 2 modules of 64Mb UCCC ICs in any bank configuration, surely?

 

[tommy2q]

try relaxing your ram timings

 

[5t3v0]

Originally posted by: tommy2q
try relaxing your ram timings

Tried the default 3-4-4-8 and 3-5-5-9 but no difference. Like I've said b4, the system has worked at 2.5GHz (280x9) and a ram freq of 229MHz with 3-3-3-6 timings at 1T on a single core cpu. Why is the dual core different?

 

[tommy2q]

maybe try 250x10 with relaxed timings and lower ram freq just to check 1t on your x2

 

[5t3v0]

Why is SuperPi slower on my X2 compared to my old Opteron 144 clocked at the same speed? The X2 is actually clocked slightly faster at 2.53GHz than the Opteron was at 2.52GHz. Is it the smaller L2 cache or the 2T command rate on my X2 system that's slowing it down?

Edit: Meant to say, 32Mb test results are as follows:

Opteron 144 @ 2.52MHz (1T) = 29m 45s
X2 4200+ @ 2.53MHz (2T) = 31m 1s

I would have expected better results on a dual-core.

Edit 2: Well after re-enabling 1T, the results are:

X2 4200+ @ 2.53MHz (1T) = 30m 2s

So the difference between 2T & 1T is 1 minute in SuperPI 32M test. I'd say it was significant. I only wish 1T was stable enough for Prime95.