Originally posted by: VirtualLarry
Originally posted by: Fox5
Just because a large percentage of the cores in a batch are defective doesn't mean all are. They only test a few, if too high a percent of those are defective, the entire batch gets chucked, even if the 20% in the middle of the wafer were fine. Or something like that.
I'm pretty sure that AMD and Intel test their chips 100%.
That's it in a nutshell. Every chip, every single chip on the wafer that reaches test, is tested for parametric yield and functional yield first and foremost.
Now there will be certain reliability flags built into the parametrics that if triggered will result in the entire wafer and/or lot to be pitched into the reclaim basket (not sold, not further binned, but entirely scrapped).
But barring the flagging of known reliability triggers, every chip that passes parametric and functional test proceeds to clockspeed test and binning.
Mixed in there somewhere (the sequence is not identical at every IDM) will be some degree of burn-in and voltage binning as well as fuse-blow (multiplier lock, redundant cache-line use, harvesting, etc).
This happens for every IC, logic of memory, analog or cmos. You can't get away with sampling and characterizing a sub-population for the purpose of determining whether the remainder of the untested population is deemed to meet specifications XYZ. IC's aren't steel or ball point pins. Way way too complicated.
(but for practicality reasons it can be cheaper to not bother testing all samples if the first handful of them are rejected, gate oxide integrity for example, if we have a single chip have a GOI issue at test we scrap the entire lot and don't bother risking sending undetected walking wounded chips into the field)
Boeing airplanes are the same way, every aspect of every single airplane to roll off an assembly line is tested to the fullest. Its not a "let's check the brakes on 1 of every 10 planes and call it day" situation.